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commit 541eabb535144214faf9dd64777c407ae502bc10 Author: Abdelatif Guettouche <abdelatif.guettou...@espressif.com> AuthorDate: Mon Apr 25 13:43:34 2022 +0200 xtensa_int_handlers.S: Refactor the calls to ps_setup. Signed-off-by: Abdelatif Guettouche <abdelatif.guettou...@espressif.com> --- arch/xtensa/src/common/xtensa_int_handlers.S | 143 +++++++++++---------------- 1 file changed, 59 insertions(+), 84 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S index 0b40e4e3ab..5f405aa8c0 100644 --- a/arch/xtensa/src/common/xtensa_int_handlers.S +++ b/arch/xtensa/src/common/xtensa_int_handlers.S @@ -121,18 +121,58 @@ g_intstacktop: #endif /**************************************************************************** - * Macro dispatch_c_isr level mask + * Macro: ps_setup * * Description: + * Set up PS for C, enable interrupts above this level and clear EXCM. * - * This will dispatch to user handlers (if any) that are registered in the - * XTOS dispatch table (_xtos_interrupt_table). These handlers would have - * been registered by calling _xtos_set_interrupt_handler(). There is one - * exception - the timer interrupt used by the OS will not be dispatched - * to a user handler - this must be handled by the caller of this macro. + * Entry Conditions: + * level - interrupt level + * tmp - scratch register * - * Level triggered and software interrupts are automatically deasserted by - * this code. + * Side Effects: + * PS and scratch register modified + * + * Assumptions: + * - PS.EXCM = 1, C calling disabled + * + ****************************************************************************/ + + .macro ps_setup level tmp + +#if 0 /* Nested interrupts no yet supported */ +# ifdef __XTENSA_CALL0_ABI__ + /* Disable interrupts at level and below */ + + movi \tmp, PS_INTLEVEL(\level) | PS_UM +# else + movi \tmp, PS_INTLEVEL(\level) | PS_UM | PS_WOE +# endif +#else +# ifdef __XTENSA_CALL0_ABI__ + /* Disable all low- and medium-priority interrupts. Nested are not yet + * supported. + */ + + movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM +# else + movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE +# endif +#endif + + wsr \tmp, PS + rsync + + .endm + +/**************************************************************************** + * Macro dispatch_c_isr level mask tmp + * + * Description: + * + * This macro will dispatch the set of pending and enabled interrupts to + * their handlers. It just does the necessary configuration and ends up + * calling xtensa_int_decode. * * Assumptions: * - PS.INTLEVEL is set to "level" at entry @@ -150,7 +190,11 @@ g_intstacktop: * ****************************************************************************/ - .macro dispatch_c_isr level mask + .macro dispatch_c_isr level mask tmp + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + + ps_setup \level \tmp #ifdef __XTENSA_CALL0_ABI__ /* Get mask of pending, enabled interrupts at this level into a2. */ @@ -233,51 +277,6 @@ g_intstacktop: 1: .endm -/**************************************************************************** - * Macro: ps_setup - * - * Description: - * Set up PS for C, enable interrupts above this level and clear EXCM. - * - * Entry Conditions: - * level - interrupt level - * tmp - scratch register - * - * Side Effects: - * PS and scratch register modified - * - * Assumptions: - * - PS.EXCM = 1, C calling disabled - * - ****************************************************************************/ - - .macro ps_setup level tmp - -#if 0 /* Nested interrupts no yet supported */ -# ifdef __XTENSA_CALL0_ABI__ - /* Disable interrupts at level and below */ - - movi \tmp, PS_INTLEVEL(\level) | PS_UM -# else - movi \tmp, PS_INTLEVEL(\level) | PS_UM | PS_WOE -# endif -#else -# ifdef __XTENSA_CALL0_ABI__ - /* Disable all low- and medium-priority interrupts. Nested are not yet - * supported. - */ - - movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM -# else - movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE -# endif -#endif - - wsr \tmp, PS - rsync - - .endm - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -322,10 +321,6 @@ _xtensa_level1_handler: setintstack a13 a14 #endif - /* Set up PS for C, enable interrupts above this level and clear EXCM. */ - - ps_setup 1 a0 - /* Decode and dispatch the interrupt. In the event of an interrupt * level context dispatch_c_isr() will (1) switch stacks to the new * thread's and (2) provide the address of the register state save @@ -333,7 +328,7 @@ _xtensa_level1_handler: * in the new thread's stack. */ - dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK + dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK a0 /* Restore registers in preparation to return from interrupt */ @@ -420,10 +415,6 @@ _xtensa_level2_handler: setintstack a13 a14 #endif - /* Set up PS for C, enable interrupts above this level and clear EXCM. */ - - ps_setup 2 a0 - /* Decode and dispatch the interrupt. In the event of an interrupt * level context dispatch_c_isr() will (1) switch stacks to the new * thread's and (2) provide the address of the register state save @@ -431,7 +422,7 @@ _xtensa_level2_handler: * in the new thread's stack. */ - dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK + dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK a0 /* Restore registers in preparation to return from interrupt */ @@ -493,10 +484,6 @@ _xtensa_level3_handler: setintstack a13 a14 #endif - /* Set up PS for C, enable interrupts above this level and clear EXCM. */ - - ps_setup 3 a0 - /* Decode and dispatch the interrupt. In the event of an interrupt * level context dispatch_c_isr() will (1) switch stacks to the new * thread's and (2) provide the address of the register state save @@ -504,7 +491,7 @@ _xtensa_level3_handler: * in the new thread's stack. */ - dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK + dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK a0 /* Restore registers in preparation to return from interrupt */ @@ -566,10 +553,6 @@ _xtensa_level4_handler: setintstack a13 a14 #endif - /* Set up PS for C, enable interrupts above this level and clear EXCM. */ - - ps_setup 4 a0 - /* Decode and dispatch the interrupt. In the event of an interrupt * level context dispatch_c_isr() will (1) switch stacks to the new * thread's and (2) provide the address of the register state save @@ -577,7 +560,7 @@ _xtensa_level4_handler: * in the new thread's stack. */ - dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK + dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK a0 /* Restore registers in preparation to return from interrupt */ @@ -639,10 +622,6 @@ _xtensa_level5_handler: setintstack a13 a14 #endif - /* Set up PS for C, enable interrupts above this level and clear EXCM. */ - - ps_setup 5 a0 - /* Decode and dispatch the interrupt. In the event of an interrupt * level context dispatch_c_isr() will (1) switch stacks to the new * thread's and (2) provide the address of the register state save @@ -650,7 +629,7 @@ _xtensa_level5_handler: * in the new thread's stack. */ - dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK + dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK a0 /* Restore registers in preparation to return from interrupt */ @@ -712,10 +691,6 @@ _xtensa_level6_handler: setintstack a13 a14 #endif - /* Set up PS for C, enable interrupts above this level and clear EXCM. */ - - ps_setup 6 a0 - /* Decode and dispatch the interrupt. In the event of an interrupt * level context dispatch_c_isr() will (1) switch stacks to the new * thread's and (2) provide the address of the register state save @@ -723,7 +698,7 @@ _xtensa_level6_handler: * in the new thread's stack. */ - dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK + dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK a0 /* Restore registers in preparation to return from interrupt */