This is an automated email from the ASF dual-hosted git repository. jerpelea pushed a commit to branch master in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 34c6bb3bd790ef725a88dd18794c20d948e7b3f5 Author: Eren Terzioglu <eren.terzio...@espressif.com> AuthorDate: Tue Jan 23 13:51:03 2024 +0300 Docs/esp32c3: esp32c3 new approach documentation added --- .../platforms/risc-v/esp32c3-legacy/index.rst | 1 + .../esp32c3-generic/ESP32-C3-DevKitC-02-v1.1.png | Bin 0 -> 1227567 bytes .../esp32c3-generic/ESP32-C3-DevKitM-1-v1.0.png | Bin 0 -> 1529086 bytes .../esp32c3/boards/esp32c3-generic/index.rst | 167 +++++++++++++++++++++ .../risc-v/{esp32c3-legacy => esp32c3}/index.rst | 35 +++-- 5 files changed, 185 insertions(+), 18 deletions(-) diff --git a/Documentation/platforms/risc-v/esp32c3-legacy/index.rst b/Documentation/platforms/risc-v/esp32c3-legacy/index.rst index ad585da475..4fdee90272 100644 --- a/Documentation/platforms/risc-v/esp32c3-legacy/index.rst +++ b/Documentation/platforms/risc-v/esp32c3-legacy/index.rst @@ -1,5 +1,6 @@ .. note:: A new approach is being adopted for this chip and this implementation will be deprecated when the same support level is achieved. + For the new approach please check :ref:`here<esp32c3>`. =========================== Espressif ESP32-C3 (Legacy) diff --git a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/ESP32-C3-DevKitC-02-v1.1.png b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/ESP32-C3-DevKitC-02-v1.1.png new file mode 100644 index 0000000000..88a8994755 Binary files /dev/null and b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/ESP32-C3-DevKitC-02-v1.1.png differ diff --git a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/ESP32-C3-DevKitM-1-v1.0.png b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/ESP32-C3-DevKitM-1-v1.0.png new file mode 100644 index 0000000000..ad0c387cc7 Binary files /dev/null and b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/ESP32-C3-DevKitM-1-v1.0.png differ diff --git a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/index.rst b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/index.rst new file mode 100644 index 0000000000..11d96d1ee8 --- /dev/null +++ b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/index.rst @@ -0,0 +1,167 @@ +================ +ESP32-C3 DevKit +================ + +The ESP32-C3 DevKit is an entry-level development board equipped with either +an ESP32-C3-WROOM-02 or an ESP32-C3-MINI-1. +ESP32-C3-WROOM-02 and ESP32-C3-MINI-1 are SoMs based on the RISC-V ESP32-C3 CPU. + +Most of the I/O pins are broken out to the pin headers on both sides for easy +interfacing. Developers can either connect peripherals with jumper wires or +mount ESP32-C3 DevKit on a breadboard. + +.. list-table:: + :align: center + + * - .. figure:: ESP32-C3-DevKitC-02-v1.1.png + :align: center + + ESP32-C3-DevKitC-02 + + - .. figure:: ESP32-C3-DevKitM-1-v1.0.png + :align: center + + ESP32-C3-DevKitM-1 + +Buttons and LEDs +================ + +Board Buttons +------------- +There are two buttons labeled Boot and RST. The RST button is not available +to software. It pulls the chip enable line that doubles as a reset line. + +The BOOT button is connected to IO9. On reset it is used as a strapping +pin to determine whether the chip boots normally or into the serial +bootloader. After reset, however, the BOOT button can be used for software +input. + +Board LEDs +---------- + +There is one on-board LED that indicates the presence of power. +Another WS2812 LED is connected to GPIO8 and is available for software. + +Configurations +============== + +All of the configurations presented below can be tested by running the following commands:: + + $ ./tools/configure.sh esp32c3-generic:<config_name> + $ make flash ESPTOOL_PORT=/dev/ttyUSB0 -j + +Where <config_name> is the name of board configuration you want to use, i.e.: nsh, buttons, wifi... +Then use a serial console terminal like ``picocom`` configured to 115200 8N1. + +coremark +-------- + +This configuration sets the CoreMark benchmark up for running on the maximum +number of cores for this system. It also enables some optimization flags and +disables the NuttShell to get the best possible score. + +.. note:: As the NSH is disabled, the application will start as soon as the + system is turned on. + +gpio +---- + +This is a test for the GPIO driver. It uses GPIO1 and GPIO2 as outputs and +GPIO9 as an interrupt pin. + +At the nsh, we can turn the outputs on and off with the following:: + + nsh> gpio -o 1 /dev/gpio0 + nsh> gpio -o 1 /dev/gpio1 + + nsh> gpio -o 0 /dev/gpio0 + nsh> gpio -o 0 /dev/gpio1 + +We can use the interrupt pin to send a signal when the interrupt fires:: + + nsh> gpio -w 14 /dev/gpio2 + +The pin is configured as a rising edge interrupt, so after issuing the +above command, connect it to 3.3V. + +nsh +--- + +Basic configuration to run the NuttShell (nsh). + +ostest +------ + +This is the NuttX test at ``apps/testing/ostest`` that is run against all new +architecture ports to assure a correct implementation of the OS. + +pwm +--- + +This configuration demonstrates the use of PWM through a LED connected to GPIO2. +To test it, just execute the ``pwm`` application:: + + nsh> pwm + pwm_main: starting output with frequency: 10000 duty: 00008000 + pwm_main: stopping output + +rtc +--- + +This configuration demonstrates the use of the RTC driver through alarms. +You can set an alarm, check its progress and receive a notification after it expires:: + + nsh> alarm 10 + alarm_daemon started + alarm_daemon: Running + Opening /dev/rtc0 + Alarm 0 set in 10 seconds + nsh> alarm -r + Opening /dev/rtc0 + Alarm 0 is active with 10 seconds to expiration + nsh> alarm_daemon: alarm 0 received + +sotest +------ + +This config is to run apps/examples/sotest. + +timer +----- + +This config test the general use purpose timers. It includes the 4 timers, +adds driver support, registers the timers as devices and includes the timer +example. + +To test it, just run the following:: + + nsh> timer -d /dev/timerx + +Where x in the timer instance. + +usbconsole +---------- + +This configuration tests the built-in USB-to-serial converter found in ESP32-C3 (revision 3). +``esptool`` can be used to check the version of the chip and if this feature is +supported. Running ``esptool.py -p <port> chip_id`` should have ``Chip is +ESP32-C3 (revision 3)`` in its output. +When connecting the board a new device should appear, a ``/dev/ttyACMX`` on Linux +or a ``/dev/cu.usbmodemXXX`` om macOS. +This can be used to flash and monitor the device with the usual commands:: + + make download ESPTOOL_PORT=/dev/ttyACM0 + minicom -D /dev/ttyACM0 + +watchdog +-------- + +This configuration tests the watchdog timers. It includes the 2 MWDTS, +adds driver support, registers the WDTs as devices and includes the watchdog +example application. + +To test it, just run the following command:: + + nsh> wdog -i /dev/watchdogX + +Where X is the watchdog instance. diff --git a/Documentation/platforms/risc-v/esp32c3-legacy/index.rst b/Documentation/platforms/risc-v/esp32c3/index.rst similarity index 96% copy from Documentation/platforms/risc-v/esp32c3-legacy/index.rst copy to Documentation/platforms/risc-v/esp32c3/index.rst index ad585da475..6902bd4a54 100644 --- a/Documentation/platforms/risc-v/esp32c3-legacy/index.rst +++ b/Documentation/platforms/risc-v/esp32c3/index.rst @@ -1,9 +1,8 @@ -.. note:: - A new approach is being adopted for this chip and this implementation will be deprecated when the same support level is achieved. +.. _esp32c3: -=========================== -Espressif ESP32-C3 (Legacy) -=========================== +================== +Espressif ESP32-C3 +================== The ESP32-C3 is an ultra-low-power and highly integrated SoC with a RISC-V core and supports 2.4 GHz Wi-Fi and Bluetooth Low Energy. @@ -146,26 +145,26 @@ The following list indicates the state of peripherals' support in NuttX: =========== ======= ===== Peripheral Support NOTES =========== ======= ===== -ADC Yes -AES Yes -Bluetooth Yes +ADC No +AES No +Bluetooth No CDC Console Yes Rev.3 -DMA Yes -eFuse Yes +DMA No +eFuse No GPIO Yes -I2C Yes +I2C No LED_PWM Yes -RNG Yes -RSA Yes +RNG No +RSA No RTC Yes -SHA Yes -SPI Yes -SPIFLASH Yes +SHA No +SPI No +SPIFLASH No Timers Yes -Touch Yes +Touch No UART Yes Watchdog Yes -Wifi Yes +Wifi No =========== ======= ===== Secure Boot and Flash Encryption