[tvm] branch main updated (24790d1d56 -> 72c60ad78a)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git from 24790d1d56 [RUNTIME][ALIGNMENT] Configurable kAllocAlignment if needed (#13307) add 72c60ad78a [AOT][FIX] Handle device contexts properly in CreateFunctionMetadata (#13392) No new revisions were added by this update. Summary of changes: src/relay/backend/aot/create_function_metadata.cc | 3 +-- tests/python/relay/aot/test_aot_create_function_metadata.py | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-)
[tvm] branch main updated (23ade0c14b -> 7cd203dc3e)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git from 23ade0c14b [TVMC] Global pass context for compile and tune (#13309) add 7cd203dc3e [TIR] Update ReductionIterNotIndexOutputBuffer to check BlockRealizeN… (#13301) No new revisions were added by this update. Summary of changes: src/tir/schedule/analysis/reducer.cc | 20 ++- ...t_tir_transform_lower_cross_thread_reduction.py | 164 + 2 files changed, 182 insertions(+), 2 deletions(-)
[tvm] branch main updated (de8a79d9ba -> ccb7d07159)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git from de8a79d9ba [skip-ci][COMMUNITY] New committer Ashutosh Parkhi (#13286) add ccb7d07159 [TIR][Arith] Use TryCompare to narrow inequalities if possible (#13024) No new revisions were added by this update. Summary of changes: src/arith/rewrite_simplify.cc | 144 + src/arith/rewrite_simplify.h | 21 +++ .../python/unittest/test_arith_rewrite_simplify.py | 2 +- tests/python/unittest/test_index_map.py| 8 +- .../test_tir_transform_inject_software_pipeline.py | 4 +- .../python/unittest/test_tir_transform_simplify.py | 46 +++ 6 files changed, 193 insertions(+), 32 deletions(-)
[tvm] branch main updated (6780c9f87d -> 7804a9886c)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git from 6780c9f87d [MetaSchedule] Tuning API cleanup & ergonomics (#12895) add 7804a9886c [Hexagon] disable cache_write schedule type from sw pipeline test (#13004) No new revisions were added by this update. Summary of changes: tests/python/contrib/test_hexagon/test_software_pipeline_async.py | 5 - 1 file changed, 4 insertions(+), 1 deletion(-)
[tvm] branch main updated (de6d806775 -> 1ea1a0bc88)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git from de6d806775 [CMSIS-NN] Support for int16 conv2d (#12950) add 1ea1a0bc88 [Hexagon] 3-stage pipeline; multi queue async DMA for cache read / write (#12954) No new revisions were added by this update. Summary of changes: src/runtime/hexagon/hexagon_device_api.cc | 6 +- src/runtime/hexagon/hexagon_user_dma.cc| 24 ++--- src/runtime/hexagon/hexagon_user_dma.h | 15 +-- src/runtime/hexagon/ring_buffer.h | 41 +++- .../cpp-runtime/hexagon/hexagon_user_dma_tests.cc | 104 +++-- tests/cpp-runtime/hexagon/ring_buffer_tests.cc | 30 +- .../test_hexagon/test_software_pipeline_async.py | 43 +++-- 7 files changed, 196 insertions(+), 67 deletions(-)
[tvm] branch main updated (f121e5e355 -> f3d3ecebe1)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git from f121e5e355 [Hexagon] [runtime] VTCM Allocator (#12947) add f3d3ecebe1 [Hexagon] vrmpy tensorization for e2e compilation of int8 models (#12911) No new revisions were added by this update. Summary of changes: python/tvm/relay/op/strategy/hexagon.py| 37 - python/tvm/topi/generic/conv2d.py | 11 +- python/tvm/topi/hexagon/__init__.py| 2 + python/tvm/topi/hexagon/conv2d.py | 49 ++- python/tvm/topi/hexagon/conv2d_alter_op.py | 111 +++ python/tvm/topi/hexagon/dense.py | 73 +- python/tvm/topi/hexagon/dense_alter_op.py | 147 python/tvm/topi/hexagon/injective.py | 3 +- python/tvm/topi/hexagon/tensor_intrin.py | 86 tests/python/contrib/test_hexagon/test_launcher.py | 149 - 10 files changed, 662 insertions(+), 6 deletions(-) create mode 100644 python/tvm/topi/hexagon/conv2d_alter_op.py create mode 100644 python/tvm/topi/hexagon/dense_alter_op.py
[tvm] branch main updated (c3357f6820 -> fa17da22c7)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git from c3357f6820 [Relay][Op] Register some forgotten op in Python side (#12963) add fa17da22c7 [Hexagon] Support template-free meta schedule tuning (#12854) No new revisions were added by this update. Summary of changes: python/tvm/meta_schedule/default_config.py | 57 +- python/tvm/meta_schedule/tune.py | 29 ++- .../contrib/test_hexagon/test_meta_schedule.py | 212 - 3 files changed, 291 insertions(+), 7 deletions(-)
[tvm] branch main updated (5dfa8da00e -> 534378b935)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git from 5dfa8da00e [Hexagon] 2-Stage Pipeline; Lower Async TIR primitives to Hexagon User DMA (#12785) add 534378b935 [Containers] Add Array::Map (#12692) No new revisions were added by this update. Summary of changes: include/tvm/runtime/container/array.h | 198 +++- src/ir/type_functor.cc | 9 +- src/te/operation/create_primfunc.cc | 2 +- src/tir/analysis/device_constraint_utils.cc | 5 +- src/tir/ir/buffer.cc| 4 +- src/tir/ir/expr.cc | 3 +- src/tir/ir/expr_functor.cc | 14 +- src/tir/ir/functor_common.h | 3 +- src/tir/ir/index_map.cc | 5 +- src/tir/ir/specialize.cc| 19 +-- src/tir/ir/stmt_functor.cc | 3 +- src/tir/schedule/primitive/decompose_padding.cc | 15 +- src/tir/schedule/transform.cc | 8 +- src/tir/transforms/inject_virtual_thread.cc | 4 +- src/tir/transforms/lower_match_buffer.cc| 8 +- src/tir/transforms/renew_defs.cc| 37 ++--- src/tir/transforms/vectorize_loop.cc| 6 +- tests/cpp/container_test.cc | 135 18 files changed, 353 insertions(+), 125 deletions(-)
[tvm] branch main updated: [Hexagon] 2-Stage Pipeline; Lower Async TIR primitives to Hexagon User DMA (#12785)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git
The following commit(s) were added to refs/heads/main by this push:
new 5dfa8da00e [Hexagon] 2-Stage Pipeline; Lower Async TIR primitives to
Hexagon User DMA (#12785)
5dfa8da00e is described below
commit 5dfa8da00ec658934f3fc0df8eb9f41a167e1545
Author: Adam Straw
AuthorDate: Tue Sep 20 12:38:04 2022 -0700
[Hexagon] 2-Stage Pipeline; Lower Async TIR primitives to Hexagon User DMA
(#12785)
* [Hexagon] 2-Stage Pipeline; Lower Async TIR primitives to HexagonUserDMA
* save queue ID in `copy`, inspect in `wait` transform; add comments
* improve testing; parameters for shape, scope, dtype
* add log statements and adjust comments to clarify pass behavior
* generalize use_async_copy for pass enable
* use DLOG instead of LOG
* trigger ci
* trigger ci again
---
include/tvm/tir/builtin.h | 10 ++
include/tvm/tir/transform.h| 5 +
src/driver/driver_api.cc | 12 +-
src/runtime/hexagon/hexagon_device_api.cc | 25 +++
src/tir/op/builtin.cc | 6 +
src/tir/transforms/lower_async_dma.cc | 194 +
src/tir/transforms/lower_tvm_builtin.cc| 30
.../test_hexagon/test_software_pipeline_async.py | 86 +
.../test_tir_transform_inject_ptx_async_copy.py| 4 +-
.../test_tir_transform_inject_software_pipeline.py | 2 +-
10 files changed, 367 insertions(+), 7 deletions(-)
diff --git a/include/tvm/tir/builtin.h b/include/tvm/tir/builtin.h
index 12290a97c8..a1a97595bf 100644
--- a/include/tvm/tir/builtin.h
+++ b/include/tvm/tir/builtin.h
@@ -720,6 +720,16 @@ TVM_DLL const Op& texture2d_load();
*/
TVM_DLL const Op& mem_copy();
+/*!
+ * \brief Initiate a non-blocking DMA copy from source to destination
+ */
+TVM_DLL const Op& dma_copy();
+
+/*!
+ * \brief Wait until the number of DMAs in flight is less than or equal to
some maximum
+ */
+TVM_DLL const Op& dma_wait();
+
/*!
* \brief Provide a true statement that can be used for simplifications
*
diff --git a/include/tvm/tir/transform.h b/include/tvm/tir/transform.h
index fd4261e4a4..a4caeee436 100644
--- a/include/tvm/tir/transform.h
+++ b/include/tvm/tir/transform.h
@@ -485,6 +485,11 @@ TVM_DLL Pass TextureFlatten();
*/
TVM_DLL Pass LowerVtcmAlloc();
+/*!
+ * \brief Lower Async TIR primitives to DMA copy and wait builtins
+ */
+TVM_DLL Pass LowerAsyncDMA();
+
/*!
* \brief Implements a Common Subexpression Elimination (CSE) for TIR
*which introduces let-in bindings for duplicated sub-expressions.
diff --git a/src/driver/driver_api.cc b/src/driver/driver_api.cc
index e528686d96..1a617dcd49 100644
--- a/src/driver/driver_api.cc
+++ b/src/driver/driver_api.cc
@@ -50,7 +50,7 @@
TVM_REGISTER_PASS_CONFIG_OPTION("tir.disable_storage_rewrite", Bool);
TVM_REGISTER_PASS_CONFIG_OPTION("tir.is_entry_func", Bool);
TVM_REGISTER_PASS_CONFIG_OPTION("tir.add_lower_pass", Array>);
TVM_REGISTER_PASS_CONFIG_OPTION("tir.debug_keep_trivial_loop", Bool);
-TVM_REGISTER_PASS_CONFIG_OPTION("tir.use_ptx_async_copy", Bool);
+TVM_REGISTER_PASS_CONFIG_OPTION("tir.use_async_copy", Bool);
using runtime::PackedFunc;
using runtime::TVMArgs;
@@ -225,6 +225,11 @@ Array CreatePassList(bool
disable_loop_partition) {
}
// LowerVtcmAlloc must occur after any transformations that modify memory
allocation locations
pass_list.push_back(tir::transform::LowerVtcmAlloc());
+ bool use_async_copy = pass_ctx->GetConfig("tir.use_async_copy",
Bool(false)).value();
+
+ if (use_async_copy) {
+pass_list.push_back(tir::transform::LowerAsyncDMA());
+ }
pass_list.push_back(tir::transform::UnrollLoop());
// Add user-defined phase-2 passes
@@ -543,10 +548,9 @@ transform::Sequential MixedModulePassManager(IRModule
mixed_mod, Target target)
mixed_pass_list.push_back(tir::transform::InferFragment());
mixed_pass_list.push_back(tir::transform::LowerThreadAllreduce());
- bool use_ptx_async_copy =
- pass_ctx->GetConfig("tir.use_ptx_async_copy", Bool(false)).value();
+ bool use_async_copy = pass_ctx->GetConfig("tir.use_async_copy",
Bool(false)).value();
- if (use_ptx_async_copy) {
+ if (use_async_copy) {
mixed_pass_list.push_back(tir::transform::InjectPTXAsyncCopy());
}
diff --git a/src/runtime/hexagon/hexagon_device_api.cc
b/src/runtime/hexagon/hexagon_device_api.cc
index 463d9799b0..84232a6144 100644
--- a/src/runtime/hexagon/hexagon_device_api.cc
+++ b/src/runtime/hexagon/hexagon_device_api.cc
@@ -33,6 +33,7 @@
#include "../workspace_pool.h"
#include "hexagon_common.h"
+#include &quo
[tvm] branch main updated (e30ac71bde -> da7f65d9d1)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git from e30ac71bde [Arith][TIR] IntSetAnalyzer, delay intersection of IntSet until use (#12821) add da7f65d9d1 [Hexagon] Create test examples to show parallelization (#12654) No new revisions were added by this update. Summary of changes: .../contrib/test_hexagon/test_parallel_hvx.py | 230 + .../contrib/test_hexagon/test_parallel_scalar.py | 159 ++ 2 files changed, 389 insertions(+) create mode 100644 tests/python/contrib/test_hexagon/test_parallel_hvx.py create mode 100644 tests/python/contrib/test_hexagon/test_parallel_scalar.py
[tvm] branch main updated: [Hexagon] [runtime] Protect access to global HexagonBufferManager map (#12807)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git
The following commit(s) were added to refs/heads/main by this push:
new 7c96e255ce [Hexagon] [runtime] Protect access to global
HexagonBufferManager map (#12807)
7c96e255ce is described below
commit 7c96e255ce7d6d6a22b3665449ebfafb581a9fc8
Author: Janet Schneider
AuthorDate: Fri Sep 16 11:53:53 2022 -0700
[Hexagon] [runtime] Protect access to global HexagonBufferManager map
(#12807)
* Protect access to global buffer manager map
* Fix lint
---
src/runtime/hexagon/hexagon_buffer_manager.h | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/src/runtime/hexagon/hexagon_buffer_manager.h
b/src/runtime/hexagon/hexagon_buffer_manager.h
index 658a39fac8..a698b0ecb1 100644
--- a/src/runtime/hexagon/hexagon_buffer_manager.h
+++ b/src/runtime/hexagon/hexagon_buffer_manager.h
@@ -43,7 +43,10 @@ class HexagonBufferManager {
CHECK(it != hexagon_buffer_map_.end())
<< "Attempt made to free unknown or already freed dataspace
allocation";
CHECK(it->second != nullptr);
-hexagon_buffer_map_.erase(it);
+{
+ std::lock_guard lock(map_mutex_);
+ hexagon_buffer_map_.erase(it);
+}
}
/*!
* \brief Allocate a HexagonBuffer.
@@ -53,15 +56,22 @@ class HexagonBufferManager {
void* AllocateHexagonBuffer(Args&&... args) {
auto buf = std::make_unique(std::forward(args)...);
void* ptr = buf->GetPointer();
-hexagon_buffer_map_.insert({ptr, std::move(buf)});
+{
+ std::lock_guard lock(map_mutex_);
+ hexagon_buffer_map_.insert({ptr, std::move(buf)});
+}
return ptr;
}
//! \brief Returns whether the HexagonBuffer is in the map.
- size_t count(void* ptr) { return hexagon_buffer_map_.count(ptr); }
+ size_t count(void* ptr) {
+std::lock_guard lock(map_mutex_);
+return hexagon_buffer_map_.count(ptr);
+ }
//! \brief Returns an iterator to the HexagonBuffer within the map.
HexagonBuffer* find(void* ptr) {
+std::lock_guard lock(map_mutex_);
auto it = hexagon_buffer_map_.find(ptr);
if (it != hexagon_buffer_map_.end()) {
return it->second.get();
@@ -69,9 +79,18 @@ class HexagonBufferManager {
return nullptr;
}
+ //! \brief Returns whether the HexagonBufferManager has any allocations.
+ bool empty() {
+std::lock_guard lock(map_mutex_);
+return hexagon_buffer_map_.empty();
+ }
+
private:
//! \brief Contains the HexagonBuffer objects managed by this class.
std::unordered_map>
hexagon_buffer_map_;
+
+ //! \brief Protects updates to the map.
+ std::mutex map_mutex_;
};
} // namespace hexagon
[tvm] branch main updated (ef784d68e0 -> 8058423f09)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git from ef784d68e0 [MetaSchedule][Test] Migrate `check_trace` to `check_sketch` (#12764) add 8058423f09 [Hexagon] Create tests to showcase vtcm loading capabilities on Hexagon. (#12667) No new revisions were added by this update. Summary of changes: python/tvm/contrib/hexagon/session.py | 2 +- src/runtime/hexagon/hexagon_buffer.cc | 9 +- src/runtime/hexagon/hexagon_device_api.cc | 11 + .../test_hexagon/test_parallel_hvx_load_vtcm.py| 537 + .../contrib/test_hexagon/test_vtcm_bandwidth.py| 169 +++ 5 files changed, 723 insertions(+), 5 deletions(-) create mode 100644 tests/python/contrib/test_hexagon/test_parallel_hvx_load_vtcm.py create mode 100644 tests/python/contrib/test_hexagon/test_vtcm_bandwidth.py
[tvm] branch main updated (a047e0228a -> b22b872da8)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git from a047e0228a [CI] Always install into a python venv in ci containers (#12663) add b22b872da8 [Hexagon] Add Hand written HVX conv2d (#12204) No new revisions were added by this update. Summary of changes: cmake/modules/Hexagon.cmake| 10 + include/tvm/runtime/hexagon/ops/conv2d.h | 198 + src/runtime/hexagon/ops/conv2d_fp16_hvx.cc | 489 + src/runtime/hexagon/ops/conv_utils.cc | 243 ++ .../hexagon/hexagon_fp16_utils_tests.cc| 289 .../test_hexagon/topi/test_conv2d_fp16_intrin.py | 248 +++ 6 files changed, 1477 insertions(+) create mode 100644 include/tvm/runtime/hexagon/ops/conv2d.h create mode 100644 src/runtime/hexagon/ops/conv2d_fp16_hvx.cc create mode 100644 src/runtime/hexagon/ops/conv_utils.cc create mode 100644 tests/cpp-runtime/hexagon/hexagon_fp16_utils_tests.cc create mode 100644 tests/python/contrib/test_hexagon/topi/test_conv2d_fp16_intrin.py
[tvm] branch main updated (b3edb6e227 -> 832cffa1c1)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git from b3edb6e227 [Apps] Pin android_camera TensorFlow/Keras dependency version (#12710) add 832cffa1c1 [Hexagon][Runtime] Better support for 2-tier memory (#12574) No new revisions were added by this update. Summary of changes: src/runtime/hexagon/hexagon_buffer.cc | 17 ++--- src/runtime/hexagon/hexagon_device_api.cc | 47 .../contrib/test_hexagon/test_memory_alloc.py | 85 ++ 3 files changed, 126 insertions(+), 23 deletions(-) create mode 100644 tests/python/contrib/test_hexagon/test_memory_alloc.py
[tvm] branch main updated (a571bfbbca -> 3f9f41a103)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git from a571bfbbca [TOPI] Allow conv definition to have custom kernel layout (#11936) add 3f9f41a103 [Relay] Add RecoverVirtualDeviceMap helper (#12085) No new revisions were added by this update. Summary of changes: src/relay/transforms/device_aware_visitors.cc | 35 src/relay/transforms/device_aware_visitors.h | 8 +++ tests/python/relay/test_pass_plan_devices.py | 78 +++ 3 files changed, 121 insertions(+)
[tvm] branch main updated: [TOPI, x86] Properly handle fused ops in TE softmax schedule (#12015)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a commit to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git The following commit(s) were added to refs/heads/main by this push: new c30b420f61 [TOPI, x86] Properly handle fused ops in TE softmax schedule (#12015) c30b420f61 is described below commit c30b420f61295fb60530dd01e84f8988605d72a5 Author: masahi AuthorDate: Wed Jul 13 21:08:05 2022 +0900 [TOPI, x86] Properly handle fused ops in TE softmax schedule (#12015) * fix x86 softmax fusion * properly handle the case where softmax and fuseed op having different layout * add test --- python/tvm/topi/x86/nn.py | 50 +-- tests/python/frontend/pytorch/test_forward.py | 40 + 2 files changed, 71 insertions(+), 19 deletions(-) diff --git a/python/tvm/topi/x86/nn.py b/python/tvm/topi/x86/nn.py index 5475fc772e..5fd1108811 100644 --- a/python/tvm/topi/x86/nn.py +++ b/python/tvm/topi/x86/nn.py @@ -18,6 +18,7 @@ """x86 nn operators""" from tvm import te from ..utils import traverse_inline +from .injective import schedule_injective_from_existing def _schedule_softmax(softmax_op, s, outs): @@ -48,28 +49,39 @@ def _schedule_softmax(softmax_op, s, outs): ) ) -# only parallelize outer dimensions up to axis -outer_axes = [s[softmax_op].op.axis[i] for i in range(0, axis)] -fused_outer_axes = s[softmax_op].fuse(*outer_axes) -s[softmax_op].parallel(fused_outer_axes) +output = outs[0] -# move computations with the same outer dimensions under the same root -s[max_elem].compute_at(s[softmax_op], fused_outer_axes) -s[expsum].compute_at(s[softmax_op], fused_outer_axes) +def _schedule(output_op, softmax_op): +# only parallelize outer dimensions up to axis +outer_axes = [output_op.axis[i] for i in range(0, axis)] +fused_outer_axes = s[output_op].fuse(*outer_axes) +s[output_op].parallel(fused_outer_axes) -if delta is not None: -s[exp].compute_inline() -s[delta].compute_inline() -if exp is not None: -s[exp].compute_at(s[softmax_op], fused_outer_axes) +if softmax_op != output_op: +# fuse softmax output with following elemwise ops. +s[softmax_op].compute_at(s[output_op], fused_outer_axes) -if softmax_op != outs[0].op: -# fuse softmax output with following elemwise ops. -output = outs[0] -outer_axes = [s[output].op.axis[i] for i in range(0, axis)] -fused_outer_axes = s[output].fuse(*outer_axes) -s[output].parallel(fused_outer_axes) -s[softmax_op].compute_at(s[output], fused_outer_axes) +# move computations with the same outer dimensions under the same root +s[max_elem].compute_at(s[output_op], fused_outer_axes) +s[expsum].compute_at(s[output_op], fused_outer_axes) + +if delta is not None: +s[exp].compute_inline() +s[delta].compute_inline() +if exp is not None: +s[exp].compute_at(s[output_op], fused_outer_axes) + +if list(output.shape) == list(softmax_op.output(0).shape): +_schedule(output.op, softmax_op) +else: +# This case can happen, for example, if the 4D input to softmax +# is in the NCHW layout while the fused elemwise op takes the NCHWc layout. +# Since we parallelize over outer axes up to the "axis" parameter of softmax, +# softmax and the fused op need to be in the same layout if we want to +# fuse them under the same parallel loop. +# This case can be removed if softmax supported AlterLayout. +schedule_injective_from_existing(s, output) +_schedule(softmax_op, softmax_op) def schedule_softmax(outs): diff --git a/tests/python/frontend/pytorch/test_forward.py b/tests/python/frontend/pytorch/test_forward.py index 30ba713396..cd7c50d486 100644 --- a/tests/python/frontend/pytorch/test_forward.py +++ b/tests/python/frontend/pytorch/test_forward.py @@ -4544,5 +4544,45 @@ def test_mod(): verify_model(test_fn, [torch.tensor([1, 2, 3, 4, 5]), torch.tensor(-1.5)]) +def test_softmax_fuse(): +# https://github.com/apache/tvm/issues/12001 +class Model(torch.nn.Module): +def __init__(self, nchwc_post_op=False) -> None: +super().__init__() +self.conv = torch.nn.Conv2d(3, 3, (1, 1), 1) +self.nchwc_post_op = nchwc_post_op + +@torch.no_grad() +def forward(self, x): +t0a = self.conv(x) +t0b = torch.floor(x) +t2b = torch.softmax(t0a, dim=2) + +if self.nchwc_post_op: +t3a = t0a - t0b +t4a = t2b - t0b +t6a = t3a + t4a +return t6a + +return t2b + 1 + +sh = [3,
[tvm] branch main updated: [VM] class Executable does not export symbols to dll (#11963)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git
The following commit(s) were added to refs/heads/main by this push:
new 3425ed8463 [VM] class Executable does not export symbols to dll
(#11963)
3425ed8463 is described below
commit 3425ed846308a456f98404c79f6df1693bed6377
Author: Valery Chernov
AuthorDate: Thu Jun 30 17:53:36 2022 +0300
[VM] class Executable does not export symbols to dll (#11963)
* class Executable of VM exports symbols to dll
* restart CI
Co-authored-by: Valery Chernov
---
include/tvm/runtime/vm/executable.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/tvm/runtime/vm/executable.h
b/include/tvm/runtime/vm/executable.h
index 774bca1e2d..2405b3c0ba 100644
--- a/include/tvm/runtime/vm/executable.h
+++ b/include/tvm/runtime/vm/executable.h
@@ -54,7 +54,7 @@ struct VMFunction;
* used by the virtual machine.
* - Code section, handling the VM functions and bytecode.
*/
-class Executable : public ModuleNode {
+class TVM_DLL Executable : public ModuleNode {
public:
/*!
* \brief Get a PackedFunc from an executable module.
[tvm] branch main updated (89c02358a1 -> 24b93f56fd)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git from 89c02358a1 [Relay] Plumb external codegen target via Target.current() (#11432) add 24b93f56fd [VM] check DLManagedTensor for conditions to construct NDArray (#11504) No new revisions were added by this update. Summary of changes: src/runtime/ndarray.cc | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-)
[tvm] branch main updated (aaee8aa441 -> 2a2d91077f)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git from aaee8aa441 [skip ci][ci] Disable `test_solution_consistency` (#11460) add 2a2d91077f [VM] Memory alignment check for `set_input` in Virtual Machine (#11391) No new revisions were added by this update. Summary of changes: include/tvm/runtime/ndarray.h | 23 +++ src/runtime/ndarray.cc| 21 - src/runtime/vm/vm.cc | 9 +++-- 3 files changed, 42 insertions(+), 11 deletions(-)
[tvm] branch main updated (ff54011 -> 2f7bb58)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from ff54011 [Bugfix][MetaSchedule] Fix over-simplification of Select (#10605) add 2f7bb58 [Hexagon] Generalize builtin for Nd memory alloc with storage scope and add lowering for VTCM / Hexagon (#10558) No new revisions were added by this update. Summary of changes: include/tvm/tir/builtin.h | 4 +- include/tvm/tir/transform.h| 7 ++ src/driver/driver_api.cc | 1 + src/runtime/hexagon/hexagon/hexagon_common.cc | 2 +- .../hexagon/hexagon/hexagon_device_api_v2.cc | 72 ++- .../hexagon/hexagon/hexagon_device_api_v2.h| 17 + src/runtime/opencl/opencl_device_api.cc| 30 +--- src/tir/op/builtin.cc | 2 +- src/tir/transforms/lower_tvm_builtin.cc| 34 + src/tir/transforms/lower_vtcm_alloc.cc | 80 ++ src/tir/transforms/texture_flatten.cc | 9 ++- .../contrib/test_hexagon/test_cache_read_write.py | 12 +++- 12 files changed, 235 insertions(+), 35 deletions(-) create mode 100644 src/tir/transforms/lower_vtcm_alloc.cc
[tvm] branch main updated: [Bugfix] Simultaneous layout transform and axis separators. (#10553)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git
The following commit(s) were added to refs/heads/main by this push:
new a57397e [Bugfix] Simultaneous layout transform and axis separators.
(#10553)
a57397e is described below
commit a57397e9a282a3faedf843b67a9b119a5d7ce975
Author: Eric Lunderberg
AuthorDate: Thu Mar 10 10:01:21 2022 -0600
[Bugfix] Simultaneous layout transform and axis separators. (#10553)
Previously, SchedulePostProcToPrimFunc would first generate the map
from buffer object to layout transformation, then would update buffers
with the axis separators. However, it failed to replace the buffer
objects in the layout transformation map, so the transformation
wasn't applied.
This PR correctly updates the layout transformation map, and
adds a unit test to catch this failure mode.
---
src/te/schedule/schedule_postproc_to_primfunc.cc | 11
tests/python/unittest/test_transform_layout.py | 70 +---
2 files changed, 60 insertions(+), 21 deletions(-)
diff --git a/src/te/schedule/schedule_postproc_to_primfunc.cc
b/src/te/schedule/schedule_postproc_to_primfunc.cc
index 0cf6e54..c7d5d7a 100644
--- a/src/te/schedule/schedule_postproc_to_primfunc.cc
+++ b/src/te/schedule/schedule_postproc_to_primfunc.cc
@@ -256,6 +256,9 @@ class AxisSeparatorsAttrUnwrapper : StmtExprMutator {
auto pass = AxisSeparatorsAttrUnwrapper(axis_separators_map);
write_ptr->buffer_map = pass.UpdateExternBufferMap(func->buffer_map);
write_ptr->body = pass(func->body);
+ if (auto map = func->attrs.GetAttr>>("layout_transform_map")) {
+func = WithAttr(std::move(func), "layout_transform_map",
pass.UpdateIndexMap(map.value()));
+ }
}
return func;
@@ -272,6 +275,14 @@ class AxisSeparatorsAttrUnwrapper : StmtExprMutator {
return output;
}
+ Map> UpdateIndexMap(const Map>& orig) {
+Map> output;
+for (const auto& kv : orig) {
+ output.Set(GetRemappedBuffer(kv.first), kv.second);
+}
+return output;
+ }
+
Stmt VisitStmt_(const AttrStmtNode* op) final {
auto ret = StmtExprMutator::VisitStmt_(op);
op = ret.as();
diff --git a/tests/python/unittest/test_transform_layout.py
b/tests/python/unittest/test_transform_layout.py
index 5cac01d..55266fd 100755
--- a/tests/python/unittest/test_transform_layout.py
+++ b/tests/python/unittest/test_transform_layout.py
@@ -222,28 +222,54 @@ class TestCompareAgainstExplicitReshape:
class Test2DPhysicalLayout:
transform_A = tvm.testing.parameter(
-by_dict={
-"2d_A": True,
-"1d_A": False,
-}
+"1d_A",
+"2d_A",
+"2d_rev_A",
)
transform_B = tvm.testing.parameter(
-by_dict={
-"2d_B": True,
-"1d_B": False,
-}
+"1d_B",
+"2d_B",
+"2d_rev_B",
)
@staticmethod
-def extract_loop_vars(stmt):
-output = []
+def extract_logical_indices(stmt):
+output = {}
+# Since the for loops can be reordered by the layout
+# transformation, identify the loop corresponding to each
+# pre-transformation axis based on the iteration extent.
def callback(node):
if isinstance(node, tvm.tir.For):
-output.append(node.loop_var)
+output[node.loop_var] = node.extent.value
post_order_visit(stmt, callback)
-return output[::-1]
+return sorted(output, key=output.get)
+
+def get_transform(self, name):
+name = name[:-2]
+if name == "1d":
+return None
+elif name == "2d":
+return lambda i, j, k: [i, j, te.AXIS_SEPARATOR, k]
+elif name == "2d_rev":
+return lambda i, j, k: [k, j, te.AXIS_SEPARATOR, i]
+else:
+raise ValueError(f"Unknown transformation: {name}")
+
+def transform_indices(self, name, logical_shape, logical_index_vars):
+name = name[:-2]
+
+i, j, k = logical_index_vars
+
+if name == "1d":
+return [i * (logical_shape[1] * logical_shape[2]) + j *
logical_shape[2] + k]
+elif name == "2d":
+return [i * logical_shape[1] + j, k]
+elif name == "2d_rev":
+return [k * logical_shape[1] + j, i]
+else:
+raise ValueError(f"Unknown transformation: {name}")
def test_2d_physical(self, dtype, transform_A, transform_B):
logical_shape = (2, 3, 4)
@@ -252,11 +278,13 @@ class Test2DPhysicalLayout:
s = te.create_schedule(B.op)
-if transf
[tvm] branch main updated (db14b7e -> d721d32)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a change to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git.
from db14b7e just a typo fixed (#10442)
add d721d32 [runtime] AOTExecutor implementation and c target
code-generator (#10283)
No new revisions were added by this update.
Summary of changes:
CMakeLists.txt | 8 +
include/tvm/relay/runtime.h| 6 +
include/tvm/runtime/metadata.h | 13 +-
include/tvm/runtime/module.h | 2 +
python/tvm/contrib/graph_executor.py | 2 +-
python/tvm/micro/model_library_format.py | 9 +
python/tvm/relay/backend/executor_factory.py | 10 +
python/tvm/relay/build_module.py | 82 +-
python/tvm/runtime/__init__.py | 2 +
.../common.py => runtime/executor/__init__.py} | 18 +-
python/tvm/runtime/executor/aot_executor.py| 182 ++
src/relay/backend/aot_executor_codegen.cc | 107 ++--
src/relay/backend/graph_executor_codegen.cc| 24 +-
src/relay/backend/runtime.cc | 4 +-
src/relay/backend/utils.cc | 16 +-
src/relay/backend/utils.h | 22 +-
src/runtime/aot_executor/aot_executor.cc | 197 +++
src/runtime/aot_executor/aot_executor.h| 147 +++
src/runtime/aot_executor/aot_executor_factory.cc | 132 ++
.../aot_executor_factory.h}| 60 ++---
.../{metadata_module.cc => const_loader_module.cc} | 89 +++
.../sdaccel_module.h => const_loader_module.h} | 34 +--
src/runtime/meta_data.h| 13 +-
src/runtime/metadata.cc| 71 +-
src/runtime/thread_storage_scope.h | 3 +-
src/target/build_common.h | 2 +-
src/target/metadata.h | 29 ++-
src/target/metadata_module.cc | 191 ++
src/target/source/codegen_c_host.cc| 18 ++
src/target/source/codegen_c_host.h | 1 +
src/target/source/codegen_source_base.h| 25 ++
src/target/source/source_module.cc | 279 +
src/target/source/source_module.h | 10 +-
src/tir/transforms/legalize_packed_calls.cc| 6 +
tests/cpp/aot_metadata_test.cc | 46 +++-
tests/python/relay/aot/test_c_device_api.py| 29 ++-
tests/python/relay/aot/test_cpp_aot.py | 197 +++
tests/python/relay/aot/test_crt_aot.py | 10 +-
.../unittest/test_aot_legalize_packed_call.py | 9 +
39 files changed, 1867 insertions(+), 238 deletions(-)
copy python/tvm/{topi/arm_cpu/mprofile/dsp/micro_kernel/common.py =>
runtime/executor/__init__.py} (69%)
create mode 100644 python/tvm/runtime/executor/aot_executor.py
create mode 100644 src/runtime/aot_executor/aot_executor.cc
create mode 100644 src/runtime/aot_executor/aot_executor.h
create mode 100644 src/runtime/aot_executor/aot_executor_factory.cc
copy src/runtime/{graph_executor/graph_executor_factory.h =>
aot_executor/aot_executor_factory.h} (59%)
rename src/runtime/{metadata_module.cc => const_loader_module.cc} (67%)
copy src/runtime/{opencl/sdaccel/sdaccel_module.h => const_loader_module.h}
(55%)
create mode 100644 tests/python/relay/aot/test_cpp_aot.py
[tvm] branch main updated: [runtime] Add Metadata classes for AOTExecutor (#10282)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git
The following commit(s) were added to refs/heads/main by this push:
new 33082e0 [runtime] Add Metadata classes for AOTExecutor (#10282)
33082e0 is described below
commit 33082e0032fb57b0516ad7e3eabd11fe0203437e
Author: Andrew Reusch
AuthorDate: Tue Feb 22 09:34:23 2022 -0800
[runtime] Add Metadata classes for AOTExecutor (#10282)
* Add new Metadata classes and base implementation.
* These were autogenerated in the original PR, but checking them in
as plain code until we can revisit the auto-generator approach.
* address masa comments
* Add documentation per Manupa's comments, and move kMetadataVersion
namespace.
* remove get_name function, used for debugging
* clang-format
---
include/tvm/runtime/metadata.h | 160
include/tvm/runtime/metadata_base.h | 198 ++
include/tvm/support/span.h | 103
src/runtime/metadata.cc | 56 +
src/target/metadata.cc | 47 +++
src/target/metadata.h | 173 ++
tests/cpp/aot_metadata_test.cc | 236
7 files changed, 973 insertions(+)
diff --git a/include/tvm/runtime/metadata.h b/include/tvm/runtime/metadata.h
new file mode 100644
index 000..b716d41
--- /dev/null
+++ b/include/tvm/runtime/metadata.h
@@ -0,0 +1,160 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/*!
+ * \file tvm/runtime/metadata.h
+ * \brief Defines types which can be used in Metadata.
+ */
+#ifndef TVM_RUNTIME_METADATA_H_
+#define TVM_RUNTIME_METADATA_H_
+
+#include
+#ifdef __cplusplus
+#include
+#include
+#include
+#endif
+#include
+#ifdef __cplusplus
+#include
+#endif
+#include
+
+// Version number recorded in emitted artifacts for runtime checking.
+#define TVM_METADATA_VERSION 1
+
+namespace tvm {
+namespace runtime {
+namespace metadata {
+/*!
+ * \brief Version of metadata emitted and understood by this compiler/runtime.
+ * Should be populated into the `version` field of all TVMMetadata.
+ */
+static const constexpr int64_t kMetadataVersion = TVM_METADATA_VERSION;
+} // namespace metadata
+} // namespace runtime
+} // namespace tvm
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * \brief Top-level metadata structure. Holds all other metadata types.
+ */
+struct TVMMetadata {
+ /*! \brief Version identifier for this metadata. */
+ int64_t version;
+ /*! \brief Inputs to the AOT run_model function.
+ * The order of the elements is the same as in the arguments to run_model.
That is to say,
+ * this array specifies the first `num_inputs` arguments to run_model.
+ */
+ const struct TVMTensorInfo* inputs;
+ /*! \brief Number of elements in `inputs` array. */
+ int64_t num_inputs;
+ /*! \brief Outputs of the AOT run_model function.
+ * The order of the elements is the same as in the arguments to run_model.
That is to say,
+ * this array specifies the last `num_outputs` arguments to run_model.
+ */
+ const struct TVMTensorInfo* outputs;
+ /*! \brief Number of elements in `outputs` array. */
+ int64_t num_outputs;
+ /*! \brief Name of the model, as passed to tvm.relay.build. */
+ const char* mod_name;
+};
+
+/*!
+ * \brief Describes one tensor argument to `run_model`.
+ * NOTE: while TIR allows for other types of arguments, such as scalars, the
AOT run_model
+ * function does not currently accept these. Therefore it's not possible to
express those
+ * in this metadata. A future patch may modify this.
+ */
+struct TVMTensorInfo {
+ /*! \brief Name of the tensor, as specified in the Relay program. */
+ const char* name;
+ /*! \brief Shape of the tensor. */
+ const int64_t* shape;
+ /*! \brief Rank of this tensor. */
+ int64_t num_shape;
+ /*! \brief Data type of one element of this tensor. */
+ DLDataType dtype;
+};
+#ifdef __cplusplus
+} // extern "C"
+#include
+namespace tvm {
+namespace runtime {
+namesp
[tvm] branch main updated (0009a30 -> 2b00835)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 0009a30 [TOPI] VNNI support for int8 dense (#10230) add 2b00835 [Relay] Make DeviceAnalyzer a mixed mode visitor (#10248) No new revisions were added by this update. Summary of changes: include/tvm/relay/expr_functor.h | 15 ++- src/relay/transforms/device_planner.cc | 8 +--- tests/python/relay/test_pass_plan_devices.py | 63 +--- 3 files changed, 63 insertions(+), 23 deletions(-)
[tvm] branch main updated (f2b7e82 -> 455c02a)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from f2b7e82 [microNPU][3] Plan generation for the cascader (#9890) add 455c02a [TVMScript] Support T.buffer_decl using data pointer from Let/Allocate (#10099) No new revisions were added by this update. Summary of changes: python/tvm/script/parser.py | 32 +- python/tvm/script/tir/ty.py | 23 +++- src/printer/tvmscript_printer.cc | 126 +- tests/python/unittest/test_tvmscript_roundtrip.py | 47 4 files changed, 198 insertions(+), 30 deletions(-)
[tvm-vta] branch main updated: Port to new Chisel stable release (3.5) (#37)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm-vta.git
The following commit(s) were added to refs/heads/main by this push:
new d4a15f6 Port to new Chisel stable release (3.5) (#37)
d4a15f6 is described below
commit d4a15f627d5cc9762a82270d1be60a136e6af9c2
Author: Kevin Laeufer
AuthorDate: Thu Jan 27 13:25:39 2022 -0800
Port to new Chisel stable release (3.5) (#37)
* upgrade to stable chisel 3.5.0
* fix chiesl 3.5 warnings
* port tests to chiseltest
* change chisel hardware makefile to use sbt test to run unittests
---
hardware/chisel/Makefile | 3 +-
hardware/chisel/build.sbt | 11 +--
.../chisel/src/main/scala/core/FetchVME64.scala| 2 +-
.../chisel/src/main/scala/core/FetchWideVME.scala | 22 +++---
hardware/chisel/src/main/scala/core/LoadUop.scala | 2 -
.../chisel/src/main/scala/core/LoadUopSimple.scala | 12 +--
.../chisel/src/main/scala/core/TensorAlu.scala | 8 +-
.../src/main/scala/core/TensorLoadNarrowVME.scala | 20 ++---
.../src/main/scala/core/TensorLoadSimple.scala | 32
.../src/main/scala/core/TensorLoadWideVME.scala| 14 ++--
.../src/main/scala/core/TensorStoreNarrowVME.scala | 12 +--
.../src/main/scala/core/TensorStoreWideVME.scala | 14 ++--
.../chisel/src/main/scala/core/TensorUtil.scala| 8 --
.../chisel/src/main/scala/dpi/VTAHostDPI.scala | 4 +-
hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala | 4 -
.../chisel/src/main/scala/shell/SimShell.scala | 4 +-
hardware/chisel/src/main/scala/shell/VCR.scala | 12 +--
hardware/chisel/src/main/scala/shell/VME.scala | 23 +-
.../chisel/src/main/scala/shell/VMESimple.scala| 14 ++--
hardware/chisel/src/main/scala/test/Test.scala | 2 +-
.../scala/util/GenericParameterizedBundle.scala| 20 +
.../chisel/src/main/scala/util/SyncQueue.scala | 52 ++---
.../chisel/src/test/scala/unittest/AluTest.scala | 2 +-
.../chisel/src/test/scala/unittest/GemmTest.scala | 4 +-
.../chisel/src/test/scala/unittest/Generic.scala | 24 +++---
.../chisel/src/test/scala/unittest/Launcher.scala | 60 --
.../chisel/src/test/scala/unittest/MvmTest.scala | 3 +-
.../scala/unittest/SyncQueue2PortMemTest.scala | 4 +-
.../src/test/scala/unittest/SyncQueueTest.scala| 3 +-
.../src/test/scala/unittest/TensorAluTest.scala| 3 +-
.../test/scala/unittest/TensorGemmJsonTest.scala | 3 +-
.../src/test/scala/unittest/TensorGemmTest.scala | 3 +-
.../src/test/scala/unittest/utils/TestRunner.scala | 91 --
33 files changed, 143 insertions(+), 352 deletions(-)
diff --git a/hardware/chisel/Makefile b/hardware/chisel/Makefile
index bbff447..2d43944 100644
--- a/hardware/chisel/Makefile
+++ b/hardware/chisel/Makefile
@@ -51,7 +51,6 @@ USE_TRACE_FST = 0
USE_TRACE_DETAILED = 0
USE_THREADS = 0
VTA_LIBNAME = libvta_hw
-UNITTEST_NAME = all
CXX = g++
# A debug build with DEBUG = 1 is useful to trace the simulation with a
# debugger.
@@ -194,7 +193,7 @@ $(chisel_build_dir)/$(TOP_TEST).$(CONFIG).sv:
sbt 'runMain vta.$(CONFIG_TEST) --target-dir $(chisel_build_dir) -o
$(TOP_TEST).$(CONFIG)'
unittest:
- sbt 'test:runMain unittest.Launcher $(UNITTEST_NAME)'
+ sbt test
clean:
-rm -rf target project/target project/project test_run_dir
diff --git a/hardware/chisel/build.sbt b/hardware/chisel/build.sbt
index 49c7951..a28e29d 100644
--- a/hardware/chisel/build.sbt
+++ b/hardware/chisel/build.sbt
@@ -21,21 +21,18 @@ name := "vta"
version := "0.1.0-SNAPSHOT"
organization := "edu.washington.cs"
-scalaVersion := "2.12.13"
+scalaVersion := "2.12.15"
scalacOptions ++= Seq(
- "-Xsource:2.11",
"-language:reflectiveCalls",
"-deprecation",
"-feature",
"-Xcheckinit",
)
-resolvers += Resolver.sonatypeRepo("snapshots")
-libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.4.3"
-libraryDependencies += "edu.berkeley.cs" %% "chisel-iotesters" % "1.5.3"
+libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.5.0"
+libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.5.0"
libraryDependencies += "com.fasterxml.jackson.core" % "jackson-databind" %
"2.10.3"
libraryDependencies += "com.fasterxml.jackson.module" %%
"jackson-module-scala" % "2.10.3"
-addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.4.3" cross
CrossVersion.full)
-addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross
CrossVersion.
[tvm] branch main updated (c3ace20 -> f1501d0)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from c3ace20 [TIR][USMP] Integrating USMP to AoT Executor (#9565) add f1501d0 Disallow copy to/from external HexagonBuffer (#9930) No new revisions were added by this update. Summary of changes: src/runtime/hexagon/hexagon/hexagon_buffer.cc | 23 +-- tests/cpp/runtime/hexagon_buffer.cc | 14 ++ 2 files changed, 31 insertions(+), 6 deletions(-)
[tvm] branch main updated: Add Hexagon VTCM and discontiguous allocation support (#9525)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git
The following commit(s) were added to refs/heads/main by this push:
new 2b35cfd Add Hexagon VTCM and discontiguous allocation support (#9525)
2b35cfd is described below
commit 2b35cfd6ddb73afecd3f550f33881e1fdc7c3267
Author: Adam Straw
AuthorDate: Sat Dec 11 08:54:40 2021 -0800
Add Hexagon VTCM and discontiguous allocation support (#9525)
* WIP Allocation abstraction for VTCM and DDR.
* Add Hexagon VTCM and discontiguous allocation support
* differentiate between dimensions and allocations
* remove change to llvm codegen
* add integration test_add_vtcm to demo vtcm alloc
* remove cmake change
* forcing contiguous allocation in device API, for now
Co-authored-by: Chris Sullivan
---
src/runtime/hexagon/hexagon/hexagon_buffer.cc | 239 -
src/runtime/hexagon/hexagon/hexagon_buffer.h | 91 +---
src/runtime/hexagon/hexagon/hexagon_common.cc | 8 +-
src/runtime/hexagon/hexagon/hexagon_common.h | 2 +
.../hexagon/hexagon/hexagon_device_api_v2.cc | 83 ---
.../contrib/test_hexagon/rpc/test_launcher.py | 48 +
6 files changed, 352 insertions(+), 119 deletions(-)
diff --git a/src/runtime/hexagon/hexagon/hexagon_buffer.cc
b/src/runtime/hexagon/hexagon/hexagon_buffer.cc
index 38f91c8..a35759d 100644
--- a/src/runtime/hexagon/hexagon/hexagon_buffer.cc
+++ b/src/runtime/hexagon/hexagon/hexagon_buffer.cc
@@ -23,83 +23,151 @@
#include
+#include "hexagon_common.h"
+
+#if defined(__hexagon__)
+#include "HAP_compute_res.h"
+#endif
+
#include
#include
-#include "hexagon_common.h"
-
namespace tvm {
namespace runtime {
namespace hexagon {
-static size_t GetDataAlignment(const DLDataType dtype) {
- size_t align = (dtype.bits / 8) * dtype.lanes;
- if (align < kAllocAlignment) return kAllocAlignment;
- return align;
-}
+struct Allocation {
+ Allocation(size_t nbytes, size_t alignment) : nbytes_(nbytes),
alignment_(alignment) {}
+ virtual ~Allocation() {}
+ Allocation(const Allocation&) = delete;
+ Allocation& operator=(const Allocation&) = delete;
+ Allocation(Allocation&&) = delete;
+ Allocation& operator=(Allocation&&) = delete;
-HexagonBuffer::HexagonBuffer(int ndim, const int64_t* shape, DLDataType dtype,
- Optional scope) {
- // TODO(csullivan): Re-enable check on ndim <= 2 when physical layout support
- // in MakePackedAPI is added.
- // ICHECK_LE(ndim, 1) << "Hexagon currently only supports flat allocations "
- //<< "and arrays of flat allocations.";
-
- DLTensor t;
- t.shape = const_cast(shape);
- t.ndim = ndim;
- t.dtype = dtype;
- size_t nbytes = GetDataSize(t);
- size_t alignment = GetDataAlignment(dtype);
- // TODO(csullivan): Extend to support arrays of allocations.
- // Move assignment from r-value constructed flat allocation.
- *this = HexagonBuffer(nbytes, alignment, scope);
-}
+ void* data_{nullptr};
+ size_t nbytes_;
+ size_t alignment_;
+};
-HexagonBuffer::HexagonBuffer(size_t nbytes, size_t alignment, Optional
scope) {
- void* ptr = nullptr;
- int ret = posix_memalign(, alignment, nbytes);
- if (ret != 0) {
-throw std::bad_alloc();
+struct DDRAllocation : public Allocation {
+ DDRAllocation(size_t nbytes, size_t alignment) : Allocation(nbytes,
alignment) {
+#ifdef _WIN32
+data_ = _aligned_malloc(nbytes, alignment);
+CHECK(data_ != nullptr);
+#else
+int ret = posix_memalign(_, alignment, nbytes);
+CHECK_EQ(ret, 0);
+#endif
}
- allocations_.push_back(ptr);
- SetStorageScope(scope);
+ ~DDRAllocation() {
+#ifdef _WIN32
+_aligned_free(data_);
+#else
+free(data_);
+#endif
+ }
+};
+
+#if defined(__hexagon__)
+struct VTCMAllocation : public Allocation {
+ VTCMAllocation(size_t nbytes, size_t alignment) : Allocation(nbytes,
alignment) {
+compute_res_attr_t res_info;
+HEXAGON_SAFE_CALL(HAP_compute_res_attr_init(_info));
+
+// allocate nbytes of vtcm on a single page
+HEXAGON_SAFE_CALL(HAP_compute_res_attr_set_vtcm_param(_info,
/*vtcm_size = */ nbytes,
+ /*b_single_page = */
1));
+context_id_ = HAP_compute_res_acquire(_info, /*timeout = */ 1);
+
+if (context_id_) {
+ data_ = HAP_compute_res_attr_get_vtcm_ptr(_info);
+ if (!data_) {
+HEXAGON_PRINT(ERROR, "ERROR: Allocated VTCM ptr is null.");
+HEXAGON_SAFE_CALL(HAP_compute_res_release(context_id_));
+return;
+ }
+} else {
+ HEXAGON_PRINT(ERROR, "ERROR: Unable to acquire requeisted resource.");
+ return;
+}
+// HEXAGON_PRINT(ALWAYS, "VTC
[tvm] branch main updated (4efec38 -> 9c4e9ff)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 4efec38 Improve the keras frontend to support tflite 2.6 (#9562) add 9c4e9ff [ONNX] Add MatMulInteger16 contrib op (#9186) No new revisions were added by this update. Summary of changes: python/tvm/relay/frontend/onnx.py | 164 - python/tvm/relay/op/strategy/cuda.py | 2 +- tests/python/frontend/onnx/test_forward.py | 42 3 files changed, 133 insertions(+), 75 deletions(-)
[tvm] branch main updated (45af5c7 -> 34ea319)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 45af5c7 [Frontend][ONNX] Support RandomNormal operator (#9493) add 34ea319 [Relay] Prepare DeadCodeElimination for running post LowerTEPass/ManifestAlloc. (#9542) No new revisions were added by this update. Summary of changes: include/tvm/relay/transform.h | 24 +- python/tvm/relay/transform/transform.py| 8 +- src/relay/op/memory/memory.cc | 12 +- src/relay/op/memory/memory.h | 2 + src/relay/op/vm/vm.cc | 19 +- src/relay/transforms/dead_code.cc | 614 + tests/python/relay/test_op_level10.py | 22 +- .../relay/test_pass_dead_code_elimination.py | 181 +- tests/python/relay/test_pass_lazy_gradient_init.py | 16 +- tests/python/relay/test_pass_partial_eval.py | 21 +- tests/python/relay/test_pass_to_cps.py | 13 +- 11 files changed, 773 insertions(+), 159 deletions(-)
[tvm] branch main updated (d66a40a -> e276929)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from d66a40a [PROFILER,VM] Fix timer device type for reshape_tensor (#9518) add e276929 cleanup Hexagon conv2d tests (#9473) No new revisions were added by this update. Summary of changes: tests/python/contrib/test_hexagon/conftest.py | 11 - .../python/contrib/test_hexagon/infrastructure.py | 153 +-- .../contrib/test_hexagon/test_conv2d_blocked.md| 74 ++- .../contrib/test_hexagon/test_conv2d_blocked.py| 500 - .../contrib/test_hexagon/test_conv2d_conv2d.py | 168 ++- .../contrib/test_hexagon/test_maxpool2d_blocked.py | 10 +- 6 files changed, 259 insertions(+), 657 deletions(-)
[tvm] branch main updated (37af1e7 -> 92ee99f)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 37af1e7 update ci-gpu to v0.78 (#9378) add 92ee99f refactor Hexagon conv2d tests (#9333) No new revisions were added by this update. Summary of changes: tests/python/contrib/test_hexagon/README.md| 6 +- .../python/contrib/test_hexagon/infrastructure.py | 63 +++- .../contrib/test_hexagon/test_conv2d_blocked.py| 349 - 3 files changed, 189 insertions(+), 229 deletions(-)
[tvm] branch main updated (0a5a029 -> af09ac9)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 0a5a029 [Community] @elvin-n -> Reviewer (#9321) add af09ac9 Adjust Hexagon conv2d schedule to split channel out (k) and move to outer loop (#9287) No new revisions were added by this update. Summary of changes: tests/python/contrib/test_hexagon/README.md| 448 - .../contrib/test_hexagon/test_conv2d_blocked.py| 86 +++- 2 files changed, 346 insertions(+), 188 deletions(-)
[tvm] branch main updated: [Tutorial] Fix vta vision detection tutorial 'sphinx' style error. (#9279)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a commit to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git The following commit(s) were added to refs/heads/main by this push: new 2177632 [Tutorial] Fix vta vision detection tutorial 'sphinx' style error. (#9279) 2177632 is described below commit 217763279371bc8eec4b61152e8b2deaef4b8a8c Author: Hua Jiang AuthorDate: Thu Oct 14 06:52:41 2021 -0700 [Tutorial] Fix vta vision detection tutorial 'sphinx' style error. (#9279) Issue: Some bash code in this tutorial does not get syntax highlighting because of the format errors. Solution: Fix the 'sphinx' 'rst' style error. --- vta/tutorials/frontend/deploy_detection.py | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/vta/tutorials/frontend/deploy_detection.py b/vta/tutorials/frontend/deploy_detection.py index 7718018..cbd22a7 100644 --- a/vta/tutorials/frontend/deploy_detection.py +++ b/vta/tutorials/frontend/deploy_detection.py @@ -34,15 +34,15 @@ tensorization in the core) to massage the compute graph for the hardware target. # # .. code-block:: bash # -# pip3 install "Pillow<7" +# pip3 install "Pillow<7" # # YOLO-V3-tiny Model with Darknet parsing have dependancy with CFFI and CV2 library, # we need to install CFFI and CV2 before executing this script. # -# pip3 install "Pillow<7" +# .. code-block:: bash # -# pip3 install cffi -# pip3 install opencv-python +# pip3 install cffi +# pip3 install opencv-python # # Now return to the python code. Import packages.
[tvm] branch main updated (8a3fcc4 -> 80beda7)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 8a3fcc4 [TVMC] Compose target options from target registry (#9218) add 80beda7 Hexagon conv2d full output slice (#9198) No new revisions were added by this update. Summary of changes: tests/python/contrib/test_hexagon/README.md| 431 + .../contrib/test_hexagon/test_conv2d_blocked.py| 117 +- 2 files changed, 529 insertions(+), 19 deletions(-) create mode 100644 tests/python/contrib/test_hexagon/README.md
[tvm] branch main updated: [TVM] Add importer for ONNX QLinearMatMul op (#8952)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git
The following commit(s) were added to refs/heads/main by this push:
new 0fa860c [TVM] Add importer for ONNX QLinearMatMul op (#8952)
0fa860c is described below
commit 0fa860c8a1a1f3c86e7ad463291d3405f3914653
Author: Christian Convey
AuthorDate: Mon Oct 11 10:06:36 2021 -0400
[TVM] Add importer for ONNX QLinearMatMul op (#8952)
* adds importer code
* enables `test_qlinearmatmul_2D` unit test
---
python/tvm/relay/frontend/common.py| 31 ++
python/tvm/relay/frontend/onnx.py | 153 +
tests/python/frontend/onnx/test_forward.py | 1 -
3 files changed, 184 insertions(+), 1 deletion(-)
diff --git a/python/tvm/relay/frontend/common.py
b/python/tvm/relay/frontend/common.py
index 3a4897a..825a586 100755
--- a/python/tvm/relay/frontend/common.py
+++ b/python/tvm/relay/frontend/common.py
@@ -835,3 +835,34 @@ def lstm_cell(
outputs_list.append(hidden_state) # [seq_num, (batch, hidden_size)]
return outputs_list, hidden_state, cell_state
+
+
+def ensure_scalar_shape(x):
+"""
+Assume that `x` is a tensor with one element (regardless of tensor rank).
+Return a version of that tensor with rank 0.
+"""
+x_shape = infer_shape(x)
+x_rank = len(x_shape)
+
+if x_rank == 0:
+return x
+
+num_elem = np.prod(x_shape)
+assert num_elem == 1, "Cannot squeeze tensor shape {} to scalar
form.".format(x_shape)
+
+return _op.squeeze(x)
+
+
+def try_resolve_var_to_const(x, graph_params):
+"""
+Try to resolve the value of tensor `x` to a specific value.
+If successful, return a Const op with that value.
+If unsuccessful, simply return `x`.
+"""
+if isinstance(x, _expr.Var) and x.name_hint in graph_params:
+value = graph_params[x.name_hint].numpy()
+dtype = infer_type(x).checked_type.dtype
+return _op.const(value, dtype)
+
+return x
diff --git a/python/tvm/relay/frontend/onnx.py
b/python/tvm/relay/frontend/onnx.py
index 86cb178..3479e1e 100644
--- a/python/tvm/relay/frontend/onnx.py
+++ b/python/tvm/relay/frontend/onnx.py
@@ -40,6 +40,7 @@ from .. import vision as _vision
from .common import (
AttrCvt,
Renamer,
+ensure_scalar_shape,
fold_constant,
get_name,
get_relay_op,
@@ -50,6 +51,7 @@ from .common import (
infer_value,
lstm_cell,
new_var,
+try_resolve_var_to_const,
unbind,
)
@@ -3506,6 +3508,156 @@ class QLinearAdd(OnnxOpConverter):
return _qnn.op.quantize(out, c_scale, c_zero_point, out_dtype=dtype)
+class QLinearMatMul(OnnxOpConverter):
+"""
+Operator converter for QLinearMatMul from Microsoft onnxruntime contrib
opset.
+
+Limitations:
+- Only supports 2D input tensors.
+- Not guaranteed to meet the integer-overflow behavior stipulated in the
+ ONNX documentation for this operator.
+"""
+
+@classmethod
+def _impl_v10(cls, inputs, attr, params):
+
+# Some of the ops used below take scalar-like inputs, and may require
either
+# of the following:
+#
+# - the input is Const node (not merely an expression that *could* be
reduced
+# to a single Const at graph-compilation time)
+#
+# - the input has a specific dtype
+#
+# This function attempts to present 'x' in a form that meets both of
those
+# requirements.
+def try_resolve_to_const_scalar(x, dtype_override=None):
+x2 = try_resolve_var_to_const(x, params)
+x3 = ensure_scalar_shape(x2)
+
+x_dtype = infer_type(x).checked_type.dtype
+if (dtype_override is not None) and (dtype_override != x_dtype):
+x4 = _op.cast(x3, dtype_override)
+else:
+x4 = x3
+
+x5 = fold_constant(x4)
+return x5
+
+# Unpack the inputs and obtain some type info...
+a, a_scale, a_zp, b, b_scale, b_zp, y_scale, y_zp = inputs
+
+a_type = infer_type(a).checked_type # 'T1' in ONNX doc for this op
+a_scale_type = infer_type(a_scale).checked_type
+a_zp_type = infer_type(a_zp).checked_type
+
+b_type = infer_type(b).checked_type # 'T2' in ONNX doc for this op
+b_scale_type = infer_type(b_scale).checked_type
+b_zp_type = infer_type(b_zp).checked_type
+
+y_scale_type = infer_type(y_scale).checked_type
+y_zp_type = infer_type(y_zp).checked_type # 'T3' in ONNX doc for this
op
+
+a_shape = infer_shape(a)
+b_shape = infer_shape(b)
+
+# Verify type assumptions, based on the ONNX doc for this op...
+assert a_type.dtype in ["int8&q
[tvm] branch main updated: [TIR] tir.transform.StorageFlatten refactor (#9091)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a commit to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git The following commit(s) were added to refs/heads/main by this push: new 659f3b7 [TIR] tir.transform.StorageFlatten refactor (#9091) 659f3b7 is described below commit 659f3b7fe10e1ca5919c554bc6eec1ba743176e2 Author: Lunderberg AuthorDate: Thu Sep 30 19:12:31 2021 -0500 [TIR] tir.transform.StorageFlatten refactor (#9091) * [TE] Improved flexibility of ArgBinder::BindDLTensor Allowed a compact DLTensor to bind to a Buffer object that defines strides, if the strides defined correspond to a compact layout. * [TIR] Exposed ElemOffset as a member function of BufferNode. * [TE] Pulled shape determination out of StorageFlattener Previously, StorageFlattener would determine the shape of a physical buffer based on the extents of the BufferRealizeNode. Pulled these out into a separate BufferShapeLegalize pass. After this pass, all buffers have a shape that matches the buffer realization extents. * [TE] Refactor stride calculation out of StorageFlattener Previously, StorageFlattener would handle any attr::dim_align annotations. Now, this is pulled out into a separate BufferStrideLegalize pass. * [TE] Refactor thread scope propagation out of StorageFlattener. Previously, StorageFlattener would use the scope in IterVar to assign a scope to allocated buffers, where not otherwise defined. This has been pulled out into a separate ThreadScopePropagate pass. * [TE] Refactor buffer bind mapping out of StorageFlattener. Previously, StorageFlattener would look for `attr::buffer_bind_scope` to determine if a Buffer object is a view into another buffer, and would apply that mapping while making the Allocate/Store/Load nodes. Now, the mapping of buffer binds is pulled out into a separate BufferStrideUnwrapper pass. This also resolves an issue in which BufferLoad/BufferStore nodes that refer to a Buffer defined through `attr::buffer_bind_scope` would generate Load/Store nodes that point to the linked buffer, rather than the actual buffer. * [TIR] Removed checks on buffer->shape.size() Even after BufferShapeLegalize, rank-zero tensors may have an empty shape. * [TIR] Relaxed check on a bufferview's striding. Original refactoring requiring that a bufferview have no explicit striding, and instead take the striding from the buffer that it is viewing. Modified to allow bufferview to specify striding, so long as it is consistent with the viewed buffer's striding. This reproduces the behavior of StorageFlatten before the refactoring. * [TIR] Fixed StorageFlatten test for shape_legalize. AttrStmtNodes that contain rewritten Buffers need to be rewritten as well. * [TIR] Assigned storage scope The earlier stage of the refactor left a buffer's storage scope undefined if it's scope was not determined by the IterVar of a loop containing its allocation. Now, these are explicitly set to StorageScope::kGlobal, to match the previous behavior of StorageFlatten. * Updated ICHECK_EQ to CHECK_EQ for a test that depends on user-provided data. * Added comments in storage_flatten.cc, indicating why buffer_bind_scope needs special handling. * Updated comment with a few examples of where compact buffers are assumed to have no strides defined. * Updated following @csullivan's comments. * Added fuzzy mapping to the BufferShapeLegalize. Maintains earlier behavior of StorageFlatten, which allows buffer views to be mapped to higher dimension buffers, if the view extent is 1 in each extra dimension. * Updated BufferShapeLegalize, asserts need to be inside the buffer_bind_scope. * Pulled all shape-dependent behavior into BufferShapeLegalize. Previously, BufferBindUnwrapper passed fuzzy_match=true to ArgBinder::BindBuffer, which could change the number of dimensions. Now, all buffer dimensions should be updated prior to BufferBindUnwrapper, and it is an error to have mismatched dimensions in BufferBindUnwrapper. * Added another pass to remove verifiable assert statements. ArgBinder::BindBuffer inserts these assert statements if they are not verifiable at the time of substitution. Previously, with one giant substitution, the assertions were verifiable at that time. After the refactor, with substitutions done in multiple stages for shape/stride/buffer_bind_scope, we need to clean up any assertions that are verifiable after all substitutions have occurred. * Minor cleanup - Removed StorageFlattener::BufferEntry::RelIndex, behav
[tvm] branch main updated (4905a8c -> 7adbb27)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a change to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git.
from 4905a8c [Torch] Support returning quantized weights and bias for BYOC
use cases (#9135)
add 7adbb27 [UnitTests] Enable minimum testing on Vulkan target in CI
(#9093)
No new revisions were added by this update.
Summary of changes:
Jenkinsfile | 2 +-
tests/scripts/task_config_build_gpu.sh | 1 +
...gpu_vulkan.sh => task_config_build_gpu_other.sh} | 4 +++-
tests/scripts/task_config_build_gpu_vulkan.sh | 21 -
tests/scripts/task_python_integration_gpuonly.sh| 2 +-
tests/scripts/task_python_unittest_gpuonly.sh | 18 --
6 files changed, 30 insertions(+), 18 deletions(-)
copy tests/scripts/{task_config_build_gpu_vulkan.sh =>
task_config_build_gpu_other.sh} (90%)
[tvm] branch main updated: [Hexagon] Don't use {} initialization with FastRPC structures (#9033)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git
The following commit(s) were added to refs/heads/main by this push:
new 1fd8f61 [Hexagon] Don't use {} initialization with FastRPC structures
(#9033)
1fd8f61 is described below
commit 1fd8f610953adc39cbd18d82f4a9e92a11575dfc
Author: Krzysztof Parzyszek
AuthorDate: Thu Sep 16 22:08:26 2021 -0500
[Hexagon] Don't use {} initialization with FastRPC structures (#9033)
The data members in FastRPC structures aren't guaranteed to remain
in the same order. Replace aggregate initialization with direct,
member-by-member initialization.
---
src/runtime/hexagon/launcher/launcher_android.cc | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/src/runtime/hexagon/launcher/launcher_android.cc
b/src/runtime/hexagon/launcher/launcher_android.cc
index c0e428c..008e4fd 100644
--- a/src/runtime/hexagon/launcher/launcher_android.cc
+++ b/src/runtime/hexagon/launcher/launcher_android.cc
@@ -32,7 +32,9 @@
#include "launcher_rpc.h"
AEEResult enable_unsigned_pd(bool enable) {
- remote_rpc_control_unsigned_module data{static_cast(enable),
CDSP_DOMAIN_ID};
+ remote_rpc_control_unsigned_module data;
+ data.domain = CDSP_DOMAIN_ID;
+ data.enable = static_cast(enable);
AEEResult rc = remote_session_control(DSPRPC_CONTROL_UNSIGNED_MODULE, ,
sizeof(data));
if (rc != AEE_SUCCESS) {
std::cout << "error " << (enable ? "enabling" : "disabling") << " unsigned
PD\n";
@@ -41,8 +43,11 @@ AEEResult enable_unsigned_pd(bool enable) {
}
AEEResult set_remote_stack_size(int size) {
- remote_rpc_thread_params th_data{CDSP_DOMAIN_ID, -1, size};
- AEEResult rc = remote_session_control(FASTRPC_THREAD_PARAMS, _data,
sizeof(th_data));
+ remote_rpc_thread_params data;
+ data.domain = CDSP_DOMAIN_ID;
+ data.prio = -1;
+ data.stack_size = size;
+ AEEResult rc = remote_session_control(FASTRPC_THREAD_PARAMS, ,
sizeof(data));
if (rc != AEE_SUCCESS) {
std::cout << "error setting remote stack size: " << std::hex << rc << '\n';
}
[tvm] branch main updated (9bc4dc0 -> 57386a2)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 9bc4dc0 [Runtime] Pipeline Executor Initial patch. (#8702) add 57386a2 [Hexagon] Treat floats as float32 when passing args to offloaded kernels (#9010) No new revisions were added by this update. Summary of changes: src/runtime/hexagon/hexagon_module.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
[tvm] branch main updated: [Hexagon] Add contrib tests for blocked conv2d and maxpool2d (#8960)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a commit to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git The following commit(s) were added to refs/heads/main by this push: new b856d9e [Hexagon] Add contrib tests for blocked conv2d and maxpool2d (#8960) b856d9e is described below commit b856d9e1b357587f1bbb92b70606b9f6b551573d Author: Chris Sullivan AuthorDate: Tue Sep 14 14:21:47 2021 -0700 [Hexagon] Add contrib tests for blocked conv2d and maxpool2d (#8960) * Add hexagon contrib tests for blocked conv2d and maxpool2d * Restructure based on review comments --- tests/python/contrib/test_hexagon/__init__.py | 18 + tests/python/contrib/test_hexagon/conftest.py | 37 ++ .../python/contrib/test_hexagon/infrastructure.py | 88 .../contrib/test_hexagon/test_conv2d_blocked.py| 473 + .../contrib/test_hexagon/test_maxpool2d_blocked.py | 155 +++ 5 files changed, 771 insertions(+) diff --git a/tests/python/contrib/test_hexagon/__init__.py b/tests/python/contrib/test_hexagon/__init__.py new file mode 100644 index 000..58dc4cc --- /dev/null +++ b/tests/python/contrib/test_hexagon/__init__.py @@ -0,0 +1,18 @@ +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. + +""" Testing infrastructure for Hexagon """ diff --git a/tests/python/contrib/test_hexagon/conftest.py b/tests/python/contrib/test_hexagon/conftest.py new file mode 100644 index 000..0329328 --- /dev/null +++ b/tests/python/contrib/test_hexagon/conftest.py @@ -0,0 +1,37 @@ +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. + +""" Hexagon testing fixtures used to deduce testing argument +values from testing parameters """ + +import tvm +from .infrastructure import get_packed_filter_layout + + +@tvm.testing.fixture +def shape_nhwc(batch, in_channel, in_size): +return (batch, in_size, in_size, in_channel) + + +@tvm.testing.fixture +def shape_oihw(out_channel, in_channel, kernel): +return (out_channel, in_channel, kernel, kernel) + + +@tvm.testing.fixture +def shape_oihw8i32o4i(out_channel, in_channel, kernel): +return get_packed_filter_layout(out_channel, in_channel, kernel, kernel) diff --git a/tests/python/contrib/test_hexagon/infrastructure.py b/tests/python/contrib/test_hexagon/infrastructure.py new file mode 100644 index 000..193a863 --- /dev/null +++ b/tests/python/contrib/test_hexagon/infrastructure.py @@ -0,0 +1,88 @@ +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. + +""" Hexagon testing infrastructure """ + +import tvm +import
[tvm] branch main updated (aa2b37d -> 90676c4)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from aa2b37d [microTVM] Add support for AutoTVM (#8715) add 90676c4 [TIR][VM] Revert a change to lower_tvm_builtin.cc from #6126 (#8274) No new revisions were added by this update. Summary of changes: src/tir/transforms/lower_tvm_builtin.cc | 10 ++ vta/tutorials/frontend/deploy_classification.py | 6 +++--- 2 files changed, 13 insertions(+), 3 deletions(-)
[tvm-vta] branch main updated: update ci files (#36)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm-vta.git
The following commit(s) were added to refs/heads/main by this push:
new 5b53757 update ci files (#36)
5b53757 is described below
commit 5b5375729dab081bff1f4afb929a3d94784200b5
Author: Luis Vega
AuthorDate: Tue Aug 31 11:27:24 2021 -0700
update ci files (#36)
---
Jenkinsfile| 7 ---
hardware/intelfocl/README.rst | 17 +
tests/scripts/task_tvm_config_build_cpu.sh | 6 ++
tests/scripts/task_tvm_cpptest.sh | 18 --
4 files changed, 35 insertions(+), 13 deletions(-)
diff --git a/Jenkinsfile b/Jenkinsfile
index 33b16f3..de8dcd5 100644
--- a/Jenkinsfile
+++ b/Jenkinsfile
@@ -21,9 +21,10 @@
// Jenkins pipeline
// See documents at https://jenkins.io/doc/book/pipeline/jenkinsfile/
-ci_lint = "tvmai/ci-lint:v0.51"
-ci_cpu = "tvmai/ci-cpu:v0.55"
-ci_i386 = "tvmai/ci-i386:v0.52"
+ci_lint = "tlcpack/ci-lint:v0.67"
+ci_cpu = "tlcpack/ci-cpu:v0.77"
+ci_i386 = "tlcpack/ci-i386:v0.73"
+
// command to start a docker container
// NOTE: docker container provides an extra layer of isolation
diff --git a/hardware/intelfocl/README.rst b/hardware/intelfocl/README.rst
index cedd697..fafe480 100644
--- a/hardware/intelfocl/README.rst
+++ b/hardware/intelfocl/README.rst
@@ -1,3 +1,20 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Intel OpenCL for FPGA Setup
---
diff --git a/tests/scripts/task_tvm_config_build_cpu.sh
b/tests/scripts/task_tvm_config_build_cpu.sh
index e1c2126..a97ce72 100755
--- a/tests/scripts/task_tvm_config_build_cpu.sh
+++ b/tests/scripts/task_tvm_config_build_cpu.sh
@@ -26,10 +26,8 @@ cp ../cmake/config.cmake .
echo set\(USE_SORT ON\) >> config.cmake
echo set\(USE_MICRO ON\) >> config.cmake
echo set\(USE_MICRO_STANDALONE_RUNTIME ON\) >> config.cmake
-echo set\(USE_GRAPH_RUNTIME_DEBUG ON\) >> config.cmake
-echo set\(USE_VM_PROFILER ON\) >> config.cmake
-echo set\(USE_EXAMPLE_EXT_RUNTIME ON\) >> config.cmake
-echo set\(USE_LLVM llvm-config-8\) >> config.cmake
+echo set\(USE_PROFILER ON\) >> config.cmake
+echo set\(USE_LLVM llvm-config-11\) >> config.cmake
echo set\(USE_NNPACK ON\) >> config.cmake
echo set\(NNPACK_PATH /NNPACK/build/\) >> config.cmake
echo set\(USE_ANTLR ON\) >> config.cmake
diff --git a/tests/scripts/task_tvm_cpptest.sh
b/tests/scripts/task_tvm_cpptest.sh
index bd8ea77..e067b77 100755
--- a/tests/scripts/task_tvm_cpptest.sh
+++ b/tests/scripts/task_tvm_cpptest.sh
@@ -25,10 +25,16 @@ cd tvm
export LD_LIBRARY_PATH="lib:${LD_LIBRARY_PATH:-}"
-# Remove existing testcases
-rm -f build/*_test
+# to avoid CI thread throttling.
+export TVM_BIND_THREADS=0
+export OMP_NUM_THREADS=1
-make cpptest -j8
-for test in build/*_test; do
-./$test
-done
+# Build cpptest suite
+make cpptest -j2
+
+# "make crttest" requires USE_MICRO to be enabled, which is not always the
case.
+if grep crttest build/Makefile > /dev/null; then
+make crttest # NOTE: don't parallelize, due to issue with build deps.
+fi
+
+cd build && ctest --gtest_death_test_style=threadsafe && cd ..
[tvm] branch main updated (6df070a -> 400baf2)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 6df070a [ONNX][TOPI] Support select_last_index for argmin/max (#8816) add 400baf2 refactor optimize GEMM on CPU tutorial (#8825) No new revisions were added by this update. Summary of changes: tutorials/optimize/opt_gemm.py | 133 ++--- 1 file changed, 72 insertions(+), 61 deletions(-)
[tvm] branch main updated: VTA cmake change to include Verilator header for building tsim library (#8797)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git
The following commit(s) were added to refs/heads/main by this push:
new 04bdd32 VTA cmake change to include Verilator header for building
tsim library (#8797)
04bdd32 is described below
commit 04bdd32281c4ae50d086e4469fd6a9ee6f0c93b6
Author: Anton Sorokin
AuthorDate: Thu Aug 26 10:21:18 2021 -0700
VTA cmake change to include Verilator header for building tsim library
(#8797)
* VTA cmake file require Verilator include for tsim target. VTA module.cc
uses svOpenArrayHandle to send wide data through DPI
* Refactor Verialtor check conditions
* Build TSIM only for CPU target. CPU target don't use -Werror to compile
with Verilator. Jenkinsfile to have tvm_multilib_tsim defined for CPU build
target.
* remove build/libvta_tsim.so from non tsim targeting builds
* Revert to enable TSIM build i386. Revert to -Werror in CPU config. Remove
verilator CPP objects from cmake config for tsim and put them as include into
vta module.cc to avoid Verilator compilation warnings
---
Jenkinsfile | 8 +---
cmake/modules/VTA.cmake | 13 -
tests/scripts/task_config_build_arm.sh | 1 -
tests/scripts/task_config_build_gpu.sh | 1 -
tests/scripts/task_config_build_i386.sh | 2 +-
tests/scripts/task_config_build_wasm.sh | 1 -
6 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/Jenkinsfile b/Jenkinsfile
index 9eafb44..fa16292 100755
--- a/Jenkinsfile
+++ b/Jenkinsfile
@@ -73,10 +73,12 @@ tvm_runtime = "build/libtvm_runtime.so, build/config.cmake"
tvm_lib = "build/libtvm.so, " + tvm_runtime
// LLVM upstream lib
tvm_multilib = "build/libtvm.so, " +
- "build/libvta_tsim.so, " +
"build/libvta_fsim.so, " +
tvm_runtime
+tvm_multilib_tsim = "build/libvta_tsim.so, " +
+ tvm_multilib
+
// command to start a docker container
docker_run = 'docker/bash.sh'
// timeout in minutes
@@ -218,7 +220,7 @@ stage('Build') {
init_git()
sh "${docker_run} ${ci_cpu} ./tests/scripts/task_config_build_cpu.sh"
make(ci_cpu, 'build', '-j2')
-pack_lib('cpu', tvm_multilib)
+pack_lib('cpu', tvm_multilib_tsim)
timeout(time: max_time, unit: 'MINUTES') {
sh "${docker_run} ${ci_cpu} ./tests/scripts/task_ci_setup.sh"
sh "${docker_run} ${ci_cpu} ./tests/scripts/task_python_unittest.sh"
@@ -252,7 +254,7 @@ stage('Build') {
init_git()
sh "${docker_run} ${ci_i386} ./tests/scripts/task_config_build_i386.sh"
make(ci_i386, 'build', '-j2')
-pack_lib('i386', tvm_multilib)
+pack_lib('i386', tvm_multilib_tsim)
}
}
},
diff --git a/cmake/modules/VTA.cmake b/cmake/modules/VTA.cmake
index e520e62..1f9d08b 100644
--- a/cmake/modules/VTA.cmake
+++ b/cmake/modules/VTA.cmake
@@ -73,6 +73,17 @@ elseif(PYTHON)
# Cycle accurate simulator driver build
if(USE_VTA_TSIM)
+if(DEFINED ENV{VERILATOR_INC_DIR})
+ set(VERILATOR_INC_DIR $ENV{VERILATOR_INC_DIR})
+elseif (EXISTS /usr/local/share/verilator/include)
+ set(VERILATOR_INC_DIR /usr/local/share/verilator/include)
+elseif (EXISTS /usr/share/verilator/include)
+ set(VERILATOR_INC_DIR /usr/share/verilator/include)
+else()
+ message(STATUS "Verilator not found in
/usr/local/share/verilator/include")
+ message(STATUS "Verilator not found in /usr/share/verilator/include")
+ message(FATAL_ERROR "Cannot find Verilator, VERILATOR_INC_DIR is not
defined")
+endif()
# Add tsim driver sources
file(GLOB TSIM_RUNTIME_SRCS ${VTA_HW_PATH}/src/*.cc)
file(GLOB TSIM_RUNTIME_SRCS vta/runtime/*.cc)
@@ -81,7 +92,7 @@ elseif(PYTHON)
list(APPEND TSIM_RUNTIME_SRCS ${VTA_HW_PATH}/src/vmem/virtual_memory.cc)
# Target lib: vta_tsim
add_library(vta_tsim SHARED ${TSIM_RUNTIME_SRCS})
-target_include_directories(vta_tsim SYSTEM PUBLIC ${VTA_HW_PATH}/include)
+target_include_directories(vta_tsim SYSTEM PUBLIC ${VTA_HW_PATH}/include
${VERILATOR_INC_DIR} ${VERILATOR_INC_DIR}/vltstd)
target_compile_definitions(vta_tsim PUBLIC
DMLC_USE_LOGGING_LIBRARY=)
foreach(__def ${VTA_DEFINITIONS})
string(SUBSTRING ${__def} 3 -1 __strip_def)
diff --git a/tests/scripts/task_config_build_arm.sh
b/tests/scripts/task_config_build_arm.sh
index cb42b9a..47fa243 100755
--- a/tests/scripts/task_config_build_arm.sh
+++ b/tests/scripts/task_config_build_arm.sh
@@ -31,7 +31,6 @@ echo set\(USE_PROFILER ON\) >> config.cmake
echo set\(USE_LLVM llvm-config-8\) >> config.cmake
echo set\(CMAKE_CXX_COMPILER g++\) >> config.cmake
ech
[tvm] branch main updated (5a6b75d -> 4a9b5b5)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 5a6b75d [Pre-commit] Add pre-commit configuration to perform minimal checks locally (#8382) add 4a9b5b5 Update CI Lint Image Version (#8841) No new revisions were added by this update. Summary of changes: Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
[tvm] branch main updated (977bdbd -> a31ebf7)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 977bdbd Force CMake targets in top-level Makefile to run (#8840) add a31ebf7 [Hexagon] Reuse Hexagon SDK analysis across cmake files (#8822) No new revisions were added by this update. Summary of changes: cmake/config.cmake| 7 ++ cmake/modules/Hexagon.cmake | 65 ++- cmake/modules/HexagonSDK.cmake| 123 src/runtime/hexagon/sim/driver/CMakeLists.txt | 8 +- src/runtime/hexagon/target/fastrpc/CMakeLists.txt | 135 ++ 5 files changed, 207 insertions(+), 131 deletions(-) create mode 100644 cmake/modules/HexagonSDK.cmake
[tvm] branch main updated (fe0bd12 -> 5ada91b)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from fe0bd12 [Hexagon] Remove uses of LLVM from simulator runtime (#8821) add 5ada91b Add link to docs and tutorials in the README. (#8832) No new revisions were added by this update. Summary of changes: README.md | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-)
[tvm-vta] branch main updated: fix types (#34)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm-vta.git
The following commit(s) were added to refs/heads/main by this push:
new 981bf2f fix types (#34)
981bf2f is described below
commit 981bf2f32729b37b2ad302052d6c74c3734a17c9
Author: Luis Vega
AuthorDate: Sun Aug 22 18:37:22 2021 -0700
fix types (#34)
---
hardware/chisel/Makefile| 16
hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala | 2 +-
hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala | 2 +-
hardware/chisel/src/main/scala/dpi/VTASimDPI.scala | 2 +-
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/hardware/chisel/Makefile b/hardware/chisel/Makefile
index 0274c17..bbff447 100644
--- a/hardware/chisel/Makefile
+++ b/hardware/chisel/Makefile
@@ -63,7 +63,7 @@ SANITIZE = 0
CXX_MAJOR := $(shell $(CXX) -dumpversion | sed 's/\..*//')
CXX_HAS_ALIGN_NEW := $(shell [ $(CXX_MAJOR) -ge 7 ] && echo true)
-config_test = $(TOP_TEST)$(CONFIG)
+CONFIG_TEST = $(TOP_TEST)$(CONFIG)
ifndef TVM_PATH
@@ -182,16 +182,16 @@ $(lib_path): $(verilator_build_dir)/V$(TOP_TEST).cpp
$(cxx_objs)
$(CXX) $(ld_flags) $(cxx_flags) $(cxx_objs) $(patsubst
%.cpp,%.cpp.o,$(shell find $(verilator_build_dir)/*.cpp)) -o $@
verilator: $(verilator_build_dir)/V$(TOP_TEST).cpp
-$(verilator_build_dir)/V$(TOP_TEST).cpp:
$(chisel_build_dir)/$(TOP_TEST).$(CONFIG).v
+$(verilator_build_dir)/V$(TOP_TEST).cpp:
$(chisel_build_dir)/$(TOP_TEST).$(CONFIG).sv
verilator $(verilator_opt) $<
-verilog: $(chisel_build_dir)/$(TOP).$(CONFIG).v
-$(chisel_build_dir)/$(TOP).$(CONFIG).v:
- sbt 'runMain vta.$(CONFIG) --target-dir $(chisel_build_dir) --top-name
$(TOP).$(CONFIG)'
+verilog: $(chisel_build_dir)/$(TOP).$(CONFIG).sv
+$(chisel_build_dir)/$(TOP).$(CONFIG).sv:
+ sbt 'runMain vta.$(CONFIG) --target-dir $(chisel_build_dir) -o
$(TOP).$(CONFIG)'
-verilog_test: $(chisel_build_dir)/$(TOP_TEST).$(CONFIG).v
-$(chisel_build_dir)/$(TOP_TEST).$(CONFIG).v:
- sbt 'runMain vta.$(config_test) --target-dir $(chisel_build_dir)
--top-name $(TOP_TEST).$(CONFIG)'
+verilog_test: $(chisel_build_dir)/$(TOP_TEST).$(CONFIG).sv
+$(chisel_build_dir)/$(TOP_TEST).$(CONFIG).sv:
+ sbt 'runMain vta.$(CONFIG_TEST) --target-dir $(chisel_build_dir) -o
$(TOP_TEST).$(CONFIG)'
unittest:
sbt 'test:runMain unittest.Launcher $(UNITTEST_NAME)'
diff --git a/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala
b/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala
index 73ae935..5c7c5ee 100644
--- a/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala
+++ b/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala
@@ -68,7 +68,7 @@ class VTAHostDPIClient extends Bundle with VTAHostDPIParams {
class VTAHostDPI extends BlackBox with HasBlackBoxResource {
val io = IO(new Bundle {
val clock = Input(Clock())
-val reset = Input(Bool())
+val reset = Input(Reset())
val dpi = new VTAHostDPIMaster
})
addResource("/verilog/VTAHostDPI.v")
diff --git a/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala
b/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala
index c77bafd..c52260d 100644
--- a/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala
+++ b/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala
@@ -69,7 +69,7 @@ class VTAMemDPIClient extends Bundle with VTAMemDPIParams {
class VTAMemDPI extends BlackBox with HasBlackBoxResource {
val io = IO(new Bundle {
val clock = Input(Clock())
-val reset = Input(Bool())
+val reset = Input(Reset())
val dpi = new VTAMemDPIClient
})
addResource("/verilog/VTAMemDPI.v")
diff --git a/hardware/chisel/src/main/scala/dpi/VTASimDPI.scala
b/hardware/chisel/src/main/scala/dpi/VTASimDPI.scala
index 96654d2..c2e7b6b 100644
--- a/hardware/chisel/src/main/scala/dpi/VTASimDPI.scala
+++ b/hardware/chisel/src/main/scala/dpi/VTASimDPI.scala
@@ -32,7 +32,7 @@ import vta.shell._
class VTASimDPI extends BlackBox with HasBlackBoxResource {
val io = IO(new Bundle {
val clock = Input(Clock())
-val reset = Input(Bool())
+val reset = Input(Reset())
val dpi_wait = Output(Bool())
})
addResource("/verilog/VTASimDPI.v")
[tvm-vta] branch main updated (4f7d249 -> 3ec5f21)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm-vta.git. from 4f7d249 Renamed graph_runtime references to graph_executor. (#31) add 3ec5f21 Port to the latest stable Chisel release (#33) No new revisions were added by this update. Summary of changes: hardware/chisel/.gitignore | 2 + hardware/chisel/build.sbt | 69 +- .../chisel/src/main/scala/core/TensorGemm.scala| 31 +- .../chisel/src/main/scala/dpi/VTAHostDPI.scala | 2 +- hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala | 2 +- hardware/chisel/src/main/scala/dpi/VTASimDPI.scala | 2 +- .../chisel/src/main/scala/shell/SimShell.scala | 1 - .../chisel/src/main/scala/shell/XilinxShell.scala | 1 - hardware/chisel/src/main/scala/test/Test.scala | 1 - hardware/chisel/src/main/scala/vta/Configs.scala | 12 ++-- .../chisel/src/test/scala/unittest/AluTest.scala | 2 +- 11 files changed, 42 insertions(+), 83 deletions(-)
[tvm-vta] branch main updated: Renamed graph_runtime references to graph_executor. (#31)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm-vta.git
The following commit(s) were added to refs/heads/main by this push:
new 4f7d249 Renamed graph_runtime references to graph_executor. (#31)
4f7d249 is described below
commit 4f7d2497c1655354f23c108d120c4ba030244d80
Author: Lunderberg
AuthorDate: Thu Aug 19 15:38:44 2021 -0500
Renamed graph_runtime references to graph_executor. (#31)
Following TVM's rename in https://github.com/apache/tvm/pull/7653,
update to avoid errors when tvm.contrib.graph_runtime is removed
entirely.
---
apps/deploy/python_deploy.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/apps/deploy/python_deploy.py b/apps/deploy/python_deploy.py
index 2502046..4f447bb 100644
--- a/apps/deploy/python_deploy.py
+++ b/apps/deploy/python_deploy.py
@@ -26,7 +26,7 @@ import requests
import numpy as np
import tvm
-from tvm.contrib import graph_runtime, download
+from tvm.contrib import graph_executor, download
CTX = tvm.ext_dev(0)
@@ -50,7 +50,7 @@ def load_model():
lib = tvm.runtime.load_module("./build/model/lib.so")
-model = graph_runtime.create(graph, lib, CTX)
+model = graph_executor.create(graph, lib, CTX)
with open("./build/model/params.params", "rb") as paramfile:
param_bytes = paramfile.read()
[tvm] branch main updated (bca155f -> a729787)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a change to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git.
from bca155f [Target] Add __launch_bounds__ directive as part of the CUDA
code generation (#8678)
add a729787 [microTVM] Project API infrastructure (#8380)
No new revisions were added by this update.
Summary of changes:
apps/bundle_deploy/crt_config/crt_config.h | 4 +-
apps/microtvm/zephyr/aot_demo/CMakeLists.txt | 27 -
apps/microtvm/zephyr/aot_demo/README.md| 20 -
.../zephyr/aot_demo/boards/mps2_an521.conf | 28 -
.../aot_demo/boards/nrf5340dk_nrf5340_cpuapp.conf | 34 -
.../zephyr/aot_demo/boards/nucleo_l4r5zi.conf | 31 -
.../zephyr/aot_demo/boards/qemu_cortex_r5.conf | 25 -
apps/microtvm/zephyr/aot_demo/boards/qemu_x86.conf | 28 -
apps/microtvm/zephyr/aot_demo/crt/crt_config.h | 62 --
apps/microtvm/zephyr/aot_demo/prj.conf | 32 -
apps/microtvm/zephyr/aot_demo/qemu-hack| 1 -
apps/microtvm/zephyr/host_driven/CMakeLists.txt| 26 -
.../zephyr/host_driven/boards/mps2_an521.conf | 28 -
.../boards/nrf5340dk_nrf5340_cpuapp.conf | 34 -
.../zephyr/host_driven/boards/nucleo_f746zg.conf | 33 -
.../zephyr/host_driven/boards/nucleo_l4r5zi.conf | 31 -
.../zephyr/host_driven/boards/qemu_cortex_r5.conf | 25 -
.../zephyr/host_driven/boards/qemu_riscv32.conf| 32 -
.../zephyr/host_driven/boards/qemu_riscv64.conf| 28 -
.../zephyr/host_driven/boards/qemu_x86.conf| 25 -
.../host_driven/boards/stm32f746g_disco.conf | 31 -
apps/microtvm/zephyr/host_driven/prj.conf | 32 -
apps/microtvm/zephyr/host_driven/qemu-hack | 1 -
.../template_project/CMakeLists.txt.template | 49 ++
.../{host_driven => template_project}/README.md| 0
.../crt_config}/crt_config.h | 2 +-
.../zephyr/template_project/microtvm_api_server.py | 716 +++
.../qemu-hack/qemu-system-arm | 0
.../qemu-hack/qemu-system-i386 | 4 +-
.../qemu-hack/qemu-system-riscv32 | 0
.../qemu-hack/qemu-system-riscv64 | 0
.../qemu-hack/qemu-system-xilinx-aarch64 | 0
.../src => template_project/src/aot_demo}/main.c | 3 +-
.../src/aot_demo}/zephyr_uart.c| 0
.../src/aot_demo}/zephyr_uart.h| 0
.../src/host_driven}/main.c| 0
cmake/modules/StandaloneCrt.cmake | 7 +-
include/tvm/runtime/crt/rpc_common/framing.h | 2 +-
python/tvm/contrib/utils.py| 2 +-
python/tvm/micro/__init__.py | 11 +-
python/tvm/micro/artifact.py | 295
python/tvm/micro/build.py | 210 --
python/tvm/micro/compiler.py | 361 --
python/tvm/micro/contrib/__init__.py | 16 -
python/tvm/micro/contrib/base.py | 67 --
python/tvm/micro/contrib/zephyr.py | 789 -
python/tvm/micro/interface_api.py | 8 +-
python/tvm/micro/micro_binary.py | 65 --
python/tvm/micro/micro_library.py | 93 ---
python/tvm/micro/model_library_format.py | 9 +-
python/tvm/micro/project.py| 151
python/tvm/micro/project_api/client.py | 235 ++
python/tvm/micro/project_api/server.py | 776
python/tvm/micro/session.py| 24 +-
.../tvm/micro/{transport/base.py => transport.py} | 50 +-
python/tvm/micro/transport/__init__.py | 27 -
python/tvm/micro/transport/debug.py| 64 --
python/tvm/micro/transport/file_descriptor.py | 119
python/tvm/micro/transport/serial.py | 135
python/tvm/micro/transport/subprocess.py | 67 --
python/tvm/micro/transport/wakeup.py | 79 ---
python/tvm/relay/testing/byoc.py | 76 ++
src/runtime/crt/crt_config-template.h | 11 +-
src/runtime/crt/graph_executor/graph_executor.c| 27 +-
src/runtime/crt/host/Makefile | 76 ++
src/runtime/crt/host/microtvm_api_server.py| 200 ++
src/runtime/crt/microtvm_rpc_common/framing.cc | 20 +
src/runtime/{crt/host => micro}/crt_config.h | 10 +-
src/runtime/micro/micro_session.cc | 15 +-
tests/lint/check_file_type.py | 35 +-
tests/micro/zephyr/conftest.py | 29 +-
tests/micro/zephyr/test_zephyr.py | 256 +++
tests/micro/zephyr/test_zephyr_aot.py | 241 ---
tests/python/relay/aot/aot_test.mk | 26 +-
tests/pyth
[tvm] branch main updated (6b7b966 -> 07701f2)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 6b7b966 [Relay][Frontend][Onnx] Enable group_conv1d import through conv2d conversion. (#8321) add 07701f2 [UnitTests] Automatic parametrization over targets, with explicit opt-out (#8010) No new revisions were added by this update. Summary of changes: conftest.py| 20 +- python/tvm/testing.py | 600 +++-- tests/python/topi/python/test_topi_relu.py | 77 ++- tests/python/unittest/test_tvm_testing_features.py | 149 + 4 files changed, 760 insertions(+), 86 deletions(-) create mode 100644 tests/python/unittest/test_tvm_testing_features.py
[tvm-vta] branch main updated: add unittest (#29)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm-vta.git
The following commit(s) were added to refs/heads/main by this push:
new 1954ff5 add unittest (#29)
1954ff5 is described below
commit 1954ff58264384de8241cc155ffe33829f0e616a
Author: Luis Vega
AuthorDate: Tue Jun 8 17:07:35 2021 -0700
add unittest (#29)
---
tests/scripts/task_python_vta_tsim.sh | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/scripts/task_python_vta_tsim.sh
b/tests/scripts/task_python_vta_tsim.sh
index 0251915..ae9bedf 100755
--- a/tests/scripts/task_python_vta_tsim.sh
+++ b/tests/scripts/task_python_vta_tsim.sh
@@ -49,6 +49,7 @@ make -C ${VTA_HW_PATH}/hardware/chisel lint
# Build VTA chisel design and verilator simulator
echo "Building VTA chisel design..."
+make -C ${VTA_HW_PATH}/hardware/chisel unittest
make -C ${VTA_HW_PATH}/hardware/chisel cleanall
make -C ${VTA_HW_PATH}/hardware/chisel USE_THREADS=0 lib
[tvm-vta] branch main updated: Chisel Pipelined ALU (#27)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm-vta.git
The following commit(s) were added to refs/heads/main by this push:
new d5e8117 Chisel Pipelined ALU (#27)
d5e8117 is described below
commit d5e8117ce1535c527c536e115b4e58d53817b82f
Author: Abhijit Davare
AuthorDate: Mon Jun 7 18:26:41 2021 -0700
Chisel Pipelined ALU (#27)
* Remove parameter values from case class
* Add new blockOutFactor parameter with default value = 1
* Support split access
* Modify to support split interface, minor refactoring
* Use split read/write intefaces
* Pipelined ALU with split interfaces
* Modify instantiation and usage of pipelined ALU and split interfaces
* Don't use internal Random by default
* Change tester name
* Add generic tester class
* Derive from GenericTest, minor refactoring
* Test ALU index generator and pipelined ALU
* Add ASF header
* Bugfix: delay slicing index by a cycle to match SyncReadMem read delay
* Formatting, comment, and minor refactoring changes for clarity
* Fix scalastyle issues for test files
---
hardware/chisel/src/main/scala/core/Compute.scala | 103 +-
hardware/chisel/src/main/scala/core/Configs.scala | 1 +
hardware/chisel/src/main/scala/core/Core.scala | 29 +-
hardware/chisel/src/main/scala/core/LoadUop.scala | 3 +-
.../chisel/src/main/scala/core/TensorAlu.scala | 401 ++---
.../chisel/src/main/scala/core/TensorGemm.scala| 106 +++---
.../chisel/src/main/scala/core/TensorLoad.scala| 62 +++-
.../chisel/src/main/scala/core/TensorStore.scala | 28 +-
.../chisel/src/main/scala/core/TensorUtil.scala| 186 --
.../chisel/src/test/scala/unittest/AluTest.scala | 42 ++-
.../scala/unittest/Generic.scala} | 48 ++-
.../chisel/src/test/scala/unittest/Launcher.scala | 2 +-
.../src/test/scala/unittest/TensorAluTest.scala| 252 +
.../test/scala/unittest/utils/RandomArray.scala| 7 +-
14 files changed, 1042 insertions(+), 228 deletions(-)
diff --git a/hardware/chisel/src/main/scala/core/Compute.scala
b/hardware/chisel/src/main/scala/core/Compute.scala
index a1e7fad..0055a25 100644
--- a/hardware/chisel/src/main/scala/core/Compute.scala
+++ b/hardware/chisel/src/main/scala/core/Compute.scala
@@ -19,6 +19,8 @@
package vta.core
+import scala.math.pow
+
import chisel3._
import chisel3.util._
import vta.util.config._
@@ -32,7 +34,7 @@ import vta.shell._
* - Compute ALU instructions (tensorAlu module)
* - Compute GEMM instructions (tensorGemm module)
*/
-class Compute(debug: Boolean = false)(implicit p: Parameters) extends Module {
+class Compute(debug: Boolean = false)(implicit val p: Parameters) extends
Module {
val mp = p(ShellKey).memParams
val io = IO(new Bundle {
val i_post = Vec(2, Input(Bool()))
@@ -58,6 +60,9 @@ class Compute(debug: Boolean = false)(implicit p: Parameters)
extends Module {
val tensorGemm = Module(new TensorGemm)
val tensorAlu = Module(new TensorAlu)
+ // try to use the acc closest to top IO
+ val topAccGrpIdx = tensorGemm.io.acc.closestIOGrpIdx
+
val inst_q = Module(new Queue(UInt(INST_BITS.W),
p(CoreKey).instQueueEntries))
// decode
@@ -118,44 +123,102 @@ class Compute(debug: Boolean = false)(implicit p:
Parameters) extends Module {
loadUop.io.baddr := io.uop_baddr
io.vme_rd(0) <> loadUop.io.vme_rd
loadUop.io.uop.idx <> Mux(dec.io.isGemm, tensorGemm.io.uop.idx,
tensorAlu.io.uop.idx)
+ assert(!tensorGemm.io.uop.idx.valid || !tensorAlu.io.uop.idx.valid)
// acc
tensorAcc.io.start := state === sIdle & start & dec.io.isLoadAcc
tensorAcc.io.inst := inst_q.io.deq.bits
tensorAcc.io.baddr := io.acc_baddr
- tensorAcc.io.tensor.rd.idx <> Mux(dec.io.isGemm, tensorGemm.io.acc.rd.idx,
tensorAlu.io.acc.rd.idx)
- tensorAcc.io.tensor.wr <> Mux(dec.io.isGemm, tensorGemm.io.acc.wr,
tensorAlu.io.acc.wr)
+ require(tensorAcc.io.tensor.lenSplit ==
+tensorAcc.io.tensor.tensorLength, "-F- Expecting a whole batch in acc
group")
+
+ // split factor of isGemm for many groups
+ val splitFactorL0 = pow(2,log2Ceil(tensorAcc.io.tensor.splitWidth) / 2).toInt
+ val splitFactorL1 = pow(2,log2Ceil(tensorAcc.io.tensor.splitWidth)
+- log2Ceil(tensorAcc.io.tensor.splitWidth) / 2).toInt
+ require(splitFactorL0 * splitFactorL1 == tensorAcc.io.tensor.splitWidth)
+ val accRdSelectL0 = for (idx <- 0 until splitFactorL1) yield {
+// can save 1 stage on small design
+if (splitFactorL1 > 1) RegNext(dec.io.isGemm, init = false.B) else
dec.io.isGemm
+ }
+
+ for (idx <- 0 until tensorAcc.io.tensor.splitWidth) {
+tensorAcc.io.tensor.rd(idx).idx <> Mux(
+ RegNext(accRdSelectL0(idx/splitFa
[tvm-vta] branch main updated: add scalastyle to test (#28)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm-vta.git
The following commit(s) were added to refs/heads/main by this push:
new 74f23ff add scalastyle to test (#28)
74f23ff is described below
commit 74f23fff285d4f57cad4afdb05e2bff08fd71f98
Author: Luis Vega
AuthorDate: Mon Jun 7 13:31:14 2021 -0700
add scalastyle to test (#28)
---
hardware/chisel/Makefile | 1 +
hardware/chisel/scalastyle-config.xml| 6 +++---
.../chisel/src/test/scala/unittest/AluTest.scala | 10 +-
.../chisel/src/test/scala/unittest/Launcher.scala| 2 +-
.../chisel/src/test/scala/unittest/MvmTest.scala | 20 ++--
.../src/test/scala/unittest/utils/Helper.scala | 4 ++--
.../src/test/scala/unittest/utils/RandomArray.scala | 6 +++---
7 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/hardware/chisel/Makefile b/hardware/chisel/Makefile
index 049b4d4..0274c17 100644
--- a/hardware/chisel/Makefile
+++ b/hardware/chisel/Makefile
@@ -165,6 +165,7 @@ default: lint lib
lint:
sbt scalastyle
+ sbt test:scalastyle
lib: $(lib_path)
diff --git a/hardware/chisel/scalastyle-config.xml
b/hardware/chisel/scalastyle-config.xml
index ae7c8e6..1252900 100644
--- a/hardware/chisel/scalastyle-config.xml
+++ b/hardware/chisel/scalastyle-config.xml
@@ -77,7 +77,7 @@
-
+
@@ -87,7 +87,7 @@
-
+
@@ -100,7 +100,7 @@
-
+
diff --git a/hardware/chisel/src/test/scala/unittest/AluTest.scala
b/hardware/chisel/src/test/scala/unittest/AluTest.scala
index 56d81b8..a4274c2 100644
--- a/hardware/chisel/src/test/scala/unittest/AluTest.scala
+++ b/hardware/chisel/src/test/scala/unittest/AluTest.scala
@@ -34,7 +34,7 @@ class TestAluVector(c: AluVector) extends PeekPokeTester(c) {
*/
def aluRef(opcode: Int, a: Array[Int], b: Array[Int], width: Int) :
Array[Int] = {
val size = a.length
-val mask = helper.getMask(log2Ceil(width))
+val mask = Helper.getMask(log2Ceil(width))
val res = Array.fill(size) {0}
if (opcode == 1) {
@@ -61,18 +61,18 @@ class TestAluVector(c: AluVector) extends PeekPokeTester(c)
{
res(i) = if (a(i) < b(i)) a(i) else b(i)
}
}
-return res
+res
}
val num_ops = ALU_OP_NUM
for (i <- 0 until num_ops) {
// generate data based on bits
-val bits = c.aluBits
+val bits = c.io.acc_a.tensorElemBits
val dataGen = new RandomArray(c.blockOut, bits)
val op = i
val in_a = dataGen.any
val in_b = if (op != 4) dataGen.any else dataGen.negative
-val mask = helper.getMask(bits)
+val mask = Helper.getMask(bits)
val res = aluRef(op, in_a, in_b, bits)
for (i <- 0 until c.blockOut) {
@@ -97,7 +97,7 @@ class TestAluVector(c: AluVector) extends PeekPokeTester(c) {
}
if (peek(c.io.acc_y.data.valid) == BigInt(1)) {
for (i <- 0 until c.blockOut) {
- expect(c.io.acc_y.data.bits(0)(i), res(i) & mask)
+expect(c.io.acc_y.data.bits(0)(i), res(i) & mask)
}
}
}
diff --git a/hardware/chisel/src/test/scala/unittest/Launcher.scala
b/hardware/chisel/src/test/scala/unittest/Launcher.scala
index 2a1d201..2d10c52 100644
--- a/hardware/chisel/src/test/scala/unittest/Launcher.scala
+++ b/hardware/chisel/src/test/scala/unittest/Launcher.scala
@@ -47,7 +47,7 @@ object Launcher {
(c) => new TestMatrixVectorMultiplication(c)
}
},
- "alu" -> { (manager: TesterOptionsManager) =>
+"alu" -> { (manager: TesterOptionsManager) =>
Driver.execute(() => new AluVector, manager) {
(c) => new TestAluVector(c)
}
diff --git a/hardware/chisel/src/test/scala/unittest/MvmTest.scala
b/hardware/chisel/src/test/scala/unittest/MvmTest.scala
index b8af879..bd4e10c 100644
--- a/hardware/chisel/src/test/scala/unittest/MvmTest.scala
+++ b/hardware/chisel/src/test/scala/unittest/MvmTest.scala
@@ -37,13 +37,13 @@ class TestMatrixVectorMultiplication(c:
MatrixVectorMultiplication) extends Peek
val size = inp.length
val res = Array.fill(size) {0}
for (i <- 0 until size) {
-var dot = 0
-for (j <- 0 until size) {
- dot += wgt(i)(j) * inp(j)
-}
-res(i) = dot * pow(2, shift).toInt
+ var dot = 0
+ for (j <- 0 until size) {
+dot += wgt(i)(j) * inp(j)
+ }
+ res(i) = dot * pow(2, shift).toInt
}
-return res
+res
}
val cycles = 5
@@ -54,9 +54,9 @@ class TestMatrixVectorMultiplication(c:
MatrixVectorMultiplication) extends Peek
val in_a = inpGen.any
val in_b = Array.fill(c.size) { wgtGen.any }
val res = mvmRef(in_a, in_b, 0)
-val inpMask = helper.getMask(c.inpBits)
-val wgtMask = helper.ge
[tvm] branch main updated (155f669 -> b753772)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 155f669 [TVMC] Fix tvmc compile to extract target and target_host from --target (#8176) add b753772 fix UTF (#8185) No new revisions were added by this update. Summary of changes: python/tvm/driver/tvmc/compiler.py | 2 +- tests/lint/git-black.sh | 8 tests/python/frontend/tensorflow2/test_functional_models.py | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-)
[tvm] branch main updated: [BYORTL][Verilator] update ops and add MobileNet (#7972)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git
The following commit(s) were added to refs/heads/main by this push:
new dbd076a [BYORTL][Verilator] update ops and add MobileNet (#7972)
dbd076a is described below
commit dbd076a91b0ffad2a23d8ac14f17c69a686a58d1
Author: Luis Vega
AuthorDate: Tue May 18 10:05:03 2021 -0700
[BYORTL][Verilator] update ops and add MobileNet (#7972)
* update
* update vta submodule
* cpp fmt
* python fmt
* skip if tflite is not available
* fmt
* change assertion
* update comment
---
3rdparty/vta-hw| 2 +-
src/runtime/contrib/verilator/verilator_kernel.h | 5 +-
src/runtime/contrib/verilator/verilator_runtime.cc | 19 +-
src/runtime/contrib/verilator/verilator_runtime.h | 5 +-
.../contrib/test_verilator/infrastructure.py | 128 ---
.../contrib/test_verilator/test_mobilenet.py | 240 +
.../test_verilator/test_verilator_codegen.py | 67 --
.../contrib/test_verilator/test_verilator_ops.py | 191
8 files changed, 554 insertions(+), 103 deletions(-)
diff --git a/3rdparty/vta-hw b/3rdparty/vta-hw
index 4319417..dfe9f57 16
--- a/3rdparty/vta-hw
+++ b/3rdparty/vta-hw
@@ -1 +1 @@
-Subproject commit 43194178b4e570a5f1dd4f3f9d37ee16fc1b65be
+Subproject commit dfe9f572a43d41e0c1ecdf036cea97042a0febfe
diff --git a/src/runtime/contrib/verilator/verilator_kernel.h
b/src/runtime/contrib/verilator/verilator_kernel.h
index f62097c..5735329 100644
--- a/src/runtime/contrib/verilator/verilator_kernel.h
+++ b/src/runtime/contrib/verilator/verilator_kernel.h
@@ -33,9 +33,12 @@ namespace tvm {
namespace runtime {
namespace contrib {
-extern "C" TVM_DLL void verilator_add(VerilatorHandle handle, int* data, int*
weight, int* out,
+extern "C" TVM_DLL void verilator_add(VerilatorHandle handle, int* left, int*
right, int* out,
int p_h_, int p_w_);
+extern "C" TVM_DLL void verilator_bias_add(VerilatorHandle handle, int* data,
int* bias, int* out,
+ int p_n_, int p_c_, int p_h_, int
p_w_);
+
} // namespace contrib
} // namespace runtime
} // namespace tvm
diff --git a/src/runtime/contrib/verilator/verilator_runtime.cc
b/src/runtime/contrib/verilator/verilator_runtime.cc
index 5dfb844..85172d4 100644
--- a/src/runtime/contrib/verilator/verilator_runtime.cc
+++ b/src/runtime/contrib/verilator/verilator_runtime.cc
@@ -80,7 +80,7 @@ VerilatorRuntime::~VerilatorRuntime() {
auto dealloc =
reinterpret_cast(lib_->GetSymbol("VerilatorDealloc"));
ICHECK(dealloc != nullptr);
dealloc(device_);
- delete lib_;
+ lib_->~VerilatorLibrary();
}
void VerilatorRuntime::SetLibrary(const std::string& lib_path) { lib_path_ =
lib_path; }
@@ -100,7 +100,6 @@ void VerilatorRuntime::Init(const Array& consts) {
ICHECK(reset != nullptr);
read_ =
reinterpret_cast(lib_->GetSymbol("VerilatorRead"));
ICHECK(read_ != nullptr);
- add_op_ =
reinterpret_cast(lib_->GetSymbol("verilator_add"));
// alloc verilator device
device_ = alloc();
@@ -108,7 +107,7 @@ void VerilatorRuntime::Init(const Array& consts) {
// enable profiler
if (prof_enable_) prof_ = VerilatorProfiler::ThreadLocal();
- // reset verilator device.
+ // reset verilator device
reset(device_, reset_cycles_);
CHECK_EQ(consts.size(), const_idx_.size())
@@ -136,11 +135,17 @@ void VerilatorRuntime::Run() {
if (node.GetOpType() == "kernel") {
CHECK_EQ(node.GetOpType(), "kernel");
auto op_name = node.GetOpName();
+ auto entry = node.GetInputs()[0];
+ auto shape = node.GetOpShape()[entry.index_];
if ("add" == op_name) {
-auto entry = node.GetInputs()[0];
-auto shape = nodes_[entry.id_].GetOpShape()[entry.index_];
-ICHECK(add_op_ != nullptr);
-add_op_(device_, in_ptr[0], in_ptr[1], out_ptr[0], shape[0], shape[1]);
+auto add =
reinterpret_cast(lib_->GetSymbol("verilator_add"));
+ICHECK(add != nullptr);
+add(device_, in_ptr[0], in_ptr[1], out_ptr[0], shape[0], shape[1]);
+ } else if ("nn.bias_add" == op_name) {
+auto bias_add =
+
reinterpret_cast(lib_->GetSymbol("verilator_bias_add"));
+ICHECK(bias_add != nullptr);
+bias_add(device_, in_ptr[0], in_ptr[1], out_ptr[0], shape[0],
shape[3], shape[1], shape[2]);
} else {
LOG(FATAL) << "Unsupported op: " << op_name;
}
diff --git a/src/runtime/contrib/verilator/verilator_runtime.h
b/src/runtime/contrib/verilator/verilator_runtime.h
index acdaa3b..664a041
[tvm] branch main updated (76ccd8e -> 3bf65b7)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 76ccd8e sort.cc added to runtime for nms compatability (#7942) add 3bf65b7 [Fix][Runtime] Use flatBuffersBuffer_ in EdgeTPURuntime::Init() (#8034) No new revisions were added by this update. Summary of changes: src/runtime/contrib/edgetpu/edgetpu_runtime.cc | 8 +++- tests/python/contrib/test_edgetpu_runtime.py | 8 +++- 2 files changed, 14 insertions(+), 2 deletions(-)
[tvm-vta] branch main updated: [App][Verilator] change scalar add to parametric-vector-add (#26)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm-vta.git
The following commit(s) were added to refs/heads/main by this push:
new dfe9f57 [App][Verilator] change scalar add to parametric-vector-add
(#26)
dfe9f57 is described below
commit dfe9f572a43d41e0c1ecdf036cea97042a0febfe
Author: Luis Vega
AuthorDate: Mon May 3 09:36:01 2021 -0700
[App][Verilator] change scalar add to parametric-vector-add (#26)
* refactor verilator app
* update makefile variable
---
apps/verilator/README.md | 2 +-
apps/verilator/{scalar_add => add}/Makefile| 13 ++--
apps/verilator/{scalar_add => add}/src/driver.cc | 20 +++---
apps/verilator/add/src/kernel.cc | 80 ++
.../verilog/adder.v => add/verilog/add.v} | 31 ++---
.../verilator/{scalar_add => add}/verilog/driver.v | 71 +--
apps/verilator/scalar_add/src/kernel.cc| 43
7 files changed, 157 insertions(+), 103 deletions(-)
diff --git a/apps/verilator/README.md b/apps/verilator/README.md
index f4b0f69..34da6a0 100644
--- a/apps/verilator/README.md
+++ b/apps/verilator/README.md
@@ -29,6 +29,6 @@ Install Verilator (4.100 or above)
## Build
1. Build Verilator hardware library by running `make`
-2. Enable Verilator backend by setting `USE_VERILATOR_HW ON` in TVM cmake
configuration file (`config.cmake`)
+2. Enable Verilator backend by setting `USE_VERILATOR ON` in TVM cmake
configuration file (`config.cmake`)
3. Build and install TVM
diff --git a/apps/verilator/scalar_add/Makefile b/apps/verilator/add/Makefile
similarity index 87%
rename from apps/verilator/scalar_add/Makefile
rename to apps/verilator/add/Makefile
index 05513f6..ee8f065 100644
--- a/apps/verilator/scalar_add/Makefile
+++ b/apps/verilator/add/Makefile
@@ -18,20 +18,24 @@
VERILATOR_BIN := $(shell which verilator)
VERILATOR_INC_DIR := $(abspath $(dir
$(VERILATOR_BIN))/../share/verilator/include)
TOP_NAME = "Top"
+LIB_NAME = "libverilator"
VERILOG_DIR = $(abspath .)/verilog
SRC_DIR = $(abspath .)/src
-ROOT_DIR = $(abspath ..)
+ROOT_DIR = $(abspath .)
TVM_DIR = $(abspath ../../../../..)
OUT_DIR = $(abspath .)/out
+LANES = 1
+LIB_PATH = $(ROOT_DIR)/$(LIB_NAME).so
-default: $(ROOT_DIR)/libverilator.so
+default: $(LIB_PATH)
-$(ROOT_DIR)/libverilator.so: $(OUT_DIR)/$(TOP_NAME).cpp
+$(LIB_PATH): $(OUT_DIR)/$(TOP_NAME).cpp
g++ \
-std=c++14 \
-O2 \
-shared \
-fPIC \
+ -DLANES=$(LANES) \
-I$(TVM_DIR)/src/runtime/contrib/verilator \
-I$(TVM_DIR)/include \
-I$(TVM_DIR)/3rdparty/dlpack/include \
@@ -49,6 +53,7 @@ $(OUT_DIR)/$(TOP_NAME).cpp: $(VERILOG_DIR)/*.v
-Wno-STMTDLY \
-Wno-WIDTH \
-Wno-UNOPTFLAT \
+ -DLANES=$(LANES) \
--cc \
--prefix $(TOP_NAME) \
--top-module "driver" \
@@ -56,4 +61,4 @@ $(OUT_DIR)/$(TOP_NAME).cpp: $(VERILOG_DIR)/*.v
$^
clean:
- -rm -rf $(OUT_DIR)
+ -rm -rf $(OUT_DIR) *.so
diff --git a/apps/verilator/scalar_add/src/driver.cc
b/apps/verilator/add/src/driver.cc
similarity index 83%
rename from apps/verilator/scalar_add/src/driver.cc
rename to apps/verilator/add/src/driver.cc
index 8d2c0f1..49c2728 100644
--- a/apps/verilator/scalar_add/src/driver.cc
+++ b/apps/verilator/add/src/driver.cc
@@ -28,14 +28,14 @@ namespace runtime {
namespace contrib {
extern "C" VerilatorHandle VerilatorAlloc() {
- Top *top = new Top;
+ Top* top = new Top;
return static_cast(top);
}
-extern "C" void VerilatorDealloc(VerilatorHandle handle) { delete
static_cast(handle); }
+extern "C" void VerilatorDealloc(VerilatorHandle handle) { delete
static_cast(handle); }
extern "C" int VerilatorRead(VerilatorHandle handle, int id, int addr) {
- Top *top = static_cast(handle);
+ Top* top = static_cast(handle);
top->opcode = 2;
top->id = id;
top->addr = addr;
@@ -44,7 +44,7 @@ extern "C" int VerilatorRead(VerilatorHandle handle, int id,
int addr) {
}
extern "C" void VerilatorWrite(VerilatorHandle handle, int id, int addr, int
value) {
- Top *top = static_cast(handle);
+ Top* top = static_cast(handle);
top->opcode = 1;
top->id = id;
top->addr = addr;
@@ -53,12 +53,12 @@ extern "C" void VerilatorWrite(VerilatorHandle handle, int
id, int addr, int val
}
extern "C" void VerilatorReset(VerilatorHandle handle, int n) {
- Top *top = static_cast(handle);
+ Top* top = static_cast(handle);
+ top->opcode = 0;
top->clock = 0;
top->reset = 1;
main_time = 0;
- while (!Verilated::gotFinish() &&
- main_time < static_cast(n * 10)) {
+ while (!Verilated::gotFinish() && main_time <
[tvm] branch main updated (4467a9c -> c7ac5ee)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 4467a9c RelayTextPrinter is now non-recursive. ExpandDataflow refactored (#7817) add c7ac5ee [µTVM] Clone Zephyr 2.5.0 from maintenance branch (#7891) No new revisions were added by this update. Summary of changes: docker/install/ubuntu_install_zephyr.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
[tvm] branch main updated (fbdffeb -> d0a0194)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from fbdffeb Protect child process enumeration in AutoTVM (#7887) add d0a0194 [VTA][OpenCL] intelfocl (#6126) No new revisions were added by this update. Summary of changes: cmake/modules/VTA.cmake| 8 + python/tvm/autotvm/task/topi_integration.py| 11 +- python/tvm/relay/op/strategy/generic.py| 9 + python/tvm/relay/testing/tf.py | 2 +- python/tvm/topi/x86/bitserial_dense.py | 2 +- src/relay/backend/compile_engine.cc| 4 +- src/runtime/workspace_pool.cc | 1 - src/tir/transforms/lower_tvm_builtin.cc| 10 - vta/python/vta/autotvm.py | 2 +- vta/python/vta/environment.py | 4 +- vta/python/vta/program_bitstream.py| 14 +- vta/python/vta/rpc_client.py | 14 +- vta/python/vta/testing/simulator.py| 8 +- vta/python/vta/testing/utils.py| 2 +- vta/python/vta/top/graphpack.py| 2 +- vta/python/vta/top/op.py | 138 - vta/python/vta/transform.py| 6 +- vta/runtime/runtime.cc | 134 - vta/runtime/runtime.h | 2 + .../integration/test_benchmark_topi_conv2d.py | 2 +- vta/tutorials/autotvm/tune_alu_vta.py | 320 + vta/tutorials/frontend/deploy_classification.py| 27 +- vta/tutorials/vta_get_started.py | 6 +- 23 files changed, 676 insertions(+), 52 deletions(-) create mode 100644 vta/tutorials/autotvm/tune_alu_vta.py
[tvm] branch main updated: [µTVM] Zephyr: Add MPS2-AN521 board as a test platform (#7864)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
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The following commit(s) were added to refs/heads/main by this push:
new ee5da50 [µTVM] Zephyr: Add MPS2-AN521 board as a test platform (#7864)
ee5da50 is described below
commit ee5da507448c52b1412dfe54a051d25e6525c769
Author: Gustavo Romero
AuthorDate: Mon Apr 19 15:17:12 2021 -0300
[µTVM] Zephyr: Add MPS2-AN521 board as a test platform (#7864)
Now that MPS2-AN521 board is supported as a µTVM target, add it as test
platform so tests can run against it by using:
$ pytest test_zephyr.py --microtvm-platforms=mps2_an521
Signed-off-by: Gustavo Romero
---
tests/micro/zephyr/conftest.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/micro/zephyr/conftest.py b/tests/micro/zephyr/conftest.py
index 83a76e7..17aeec4 100644
--- a/tests/micro/zephyr/conftest.py
+++ b/tests/micro/zephyr/conftest.py
@@ -27,6 +27,7 @@ PLATFORMS = {
"stm32f746xx_nucleo": ("stm32f746xx", "nucleo_f746zg"),
"stm32f746xx_disco": ("stm32f746xx", "stm32f746g_disco"),
"nrf5340dk": ("nrf5340dk", "nrf5340dk_nrf5340_cpuapp"),
+"mps2_an521": ("mps2_an521", "mps2_an521-qemu"),
}
[tvm] branch main updated (8e25576 -> e67c5b7)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 8e25576 [VTA] Update vta-hw dependency (#7874) add e67c5b7 [BYOC][ACL] ACL migrated to v21.02 (#7649) No new revisions were added by this update. Summary of changes: docker/install/ubuntu_install_arm_compute_lib.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
[tvm] branch main updated: [VTA] Update vta-hw dependency (#7874)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a commit to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git The following commit(s) were added to refs/heads/main by this push: new 8e25576 [VTA] Update vta-hw dependency (#7874) 8e25576 is described below commit 8e25576711c32cc12da38904ee920a5040d944bd Author: Tianqi Chen AuthorDate: Mon Apr 19 14:05:57 2021 -0400 [VTA] Update vta-hw dependency (#7874) --- 3rdparty/vta-hw | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/vta-hw b/3rdparty/vta-hw index 87ce9ac..4319417 16 --- a/3rdparty/vta-hw +++ b/3rdparty/vta-hw @@ -1 +1 @@ -Subproject commit 87ce9acfae550d1a487746e9d06c2e250076e54c +Subproject commit 43194178b4e570a5f1dd4f3f9d37ee16fc1b65be
[tvm-vta] branch main updated: adapt chisel impl to new VTA ISA (#24)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm-vta.git
The following commit(s) were added to refs/heads/main by this push:
new 4319417 adapt chisel impl to new VTA ISA (#24)
4319417 is described below
commit 43194178b4e570a5f1dd4f3f9d37ee16fc1b65be
Author: Luis Vega
AuthorDate: Sat Apr 17 09:43:52 2021 -0700
adapt chisel impl to new VTA ISA (#24)
* adapt chisel impl to new VTA ISA
* add comment
* rename variable
* update comment
* remove comment
---
hardware/chisel/src/main/scala/core/Decode.scala| 9 -
hardware/chisel/src/main/scala/core/ISA.scala | 19 ++-
hardware/chisel/src/main/scala/core/TensorAlu.scala | 10 ++
3 files changed, 20 insertions(+), 18 deletions(-)
diff --git a/hardware/chisel/src/main/scala/core/Decode.scala
b/hardware/chisel/src/main/scala/core/Decode.scala
index 37f6ab4..dc8d3e1 100644
--- a/hardware/chisel/src/main/scala/core/Decode.scala
+++ b/hardware/chisel/src/main/scala/core/Decode.scala
@@ -43,7 +43,7 @@ class MemDecode extends Bundle {
val xstride = UInt(M_STRIDE_BITS.W)
val xsize = UInt(M_SIZE_BITS.W)
val ysize = UInt(M_SIZE_BITS.W)
- val empty_0 = UInt(7.W) // derive this
+ val empty_0 = UInt(6.W) // derive this
val dram_offset = UInt(M_DRAM_OFFSET_BITS.W)
val sram_offset = UInt(M_SRAM_OFFSET_BITS.W)
val id = UInt(M_ID_BITS.W)
@@ -90,12 +90,11 @@ class GemmDecode extends Bundle {
* - VSHX
*/
class AluDecode extends Bundle {
- val empty_1 = Bool()
val alu_imm = UInt(C_ALU_IMM_BITS.W)
val alu_use_imm = Bool()
- val alu_op = UInt(C_ALU_DEC_BITS.W)
- val src_1 = UInt(C_IIDX_BITS.W)
- val src_0 = UInt(C_IIDX_BITS.W)
+ val alu_op = UInt(C_ALU_OP_BITS.W)
+ val src_1 = UInt(C_AIDX_BITS.W)
+ val src_0 = UInt(C_AIDX_BITS.W)
val dst_1 = UInt(C_AIDX_BITS.W)
val dst_0 = UInt(C_AIDX_BITS.W)
val empty_0 = Bool()
diff --git a/hardware/chisel/src/main/scala/core/ISA.scala
b/hardware/chisel/src/main/scala/core/ISA.scala
index bfe89eb..503cc2b 100644
--- a/hardware/chisel/src/main/scala/core/ISA.scala
+++ b/hardware/chisel/src/main/scala/core/ISA.scala
@@ -33,7 +33,7 @@ trait ISAConstants {
val OP_BITS = 3
val M_DEP_BITS = 4
- val M_ID_BITS = 2
+ val M_ID_BITS = 3
val M_SRAM_OFFSET_BITS = 16
val M_DRAM_OFFSET_BITS = 32
val M_SIZE_BITS = 16
@@ -46,7 +46,7 @@ trait ISAConstants {
val C_AIDX_BITS = 11
val C_IIDX_BITS = 11
val C_WIDX_BITS = 10
- val C_ALU_DEC_BITS = 2 // FIXME: there should be a SHL and SHR instruction
+ val C_ALU_DEC_BITS = 2
val C_ALU_OP_BITS = 3
val C_ALU_IMM_BITS = 16
@@ -67,6 +67,7 @@ trait ISAConstants {
val M_ID_W = 1.asUInt(M_ID_BITS.W)
val M_ID_I = 2.asUInt(M_ID_BITS.W)
val M_ID_A = 3.asUInt(M_ID_BITS.W)
+ val M_ID_O = 4.asUInt(M_ID_BITS.W)
}
/** ISA.
@@ -82,7 +83,7 @@ object ISA {
private val depBits = 4
private val idBits: HashMap[String, Int] =
-HashMap(("task", 3), ("mem", 2), ("alu", 2))
+HashMap(("task", 3), ("mem", 3), ("alu", 3))
private val taskId: HashMap[String, String] =
HashMap(("load", "000"),
@@ -92,13 +93,13 @@ object ISA {
("alu", "100"))
private val memId: HashMap[String, String] =
-HashMap(("uop", "00"), ("wgt", "01"), ("inp", "10"), ("acc", "11"))
+HashMap(("uop", "000"), ("wgt", "001"), ("inp", "010"), ("acc", "011"),
("out", "100"))
private val aluId: HashMap[String, String] =
-HashMap(("minpool", "00"),
- ("maxpool", "01"),
- ("add", "10"),
- ("shift", "11"))
+HashMap(("minpool", "000"),
+ ("maxpool", "001"),
+ ("add", "010"),
+ ("shift", "011"))
private def dontCare(bits: Int): String = "?" * bits
@@ -124,7 +125,7 @@ object ISA {
private def alu(id: String): BitPat = {
// TODO: move alu id next to task id
-val inst = dontCare(18) + aluId(id) + dontCare(105) + taskId("alu")
+val inst = dontCare(17) + aluId(id) + dontCare(105) + taskId("alu")
instPat(inst)
}
diff --git a/hardware/chisel/src/main/scala/core/TensorAlu.scala
b/hardware/chisel/src/main/scala/core/TensorAlu.scala
index 6af3c83..81abb8e 100644
--- a/hardware/chisel/src/main/scala/core/TensorAlu.scala
+++ b/hardware/chisel/src/main/scala/core/TensorAlu.scala
@@ -39,6 +39,7 @@ class Alu(implicit p: Parameters) extends Module {
val m = ~ub(width - 1, 0) + 1.U
val n = ub(width - 1, 0
[tvm] branch main updated (2b690ad -> 76eb16f)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 2b690ad [TensorIR][M1b] Schedule class (#7847) add 76eb16f [µTVM] Zephyr: Add STM32F746 disco board as a test platform (#7863) No new revisions were added by this update. Summary of changes: tests/micro/zephyr/conftest.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
[tvm-vta] branch main updated: [CI] Fix build on main (#25)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm-vta.git
The following commit(s) were added to refs/heads/main by this push:
new b61fe13 [CI] Fix build on main (#25)
b61fe13 is described below
commit b61fe1329cd7813852de443c525f6aa99b32df3a
Author: Tianqi Chen
AuthorDate: Fri Apr 16 14:50:41 2021 -0400
[CI] Fix build on main (#25)
* [CI] Fix build on main
* Increase jenkins timeout
---
Jenkinsfile | 2 +-
tests/scripts/task_tvm_clean.sh | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Jenkinsfile b/Jenkinsfile
index 8bca45d..33b16f3 100644
--- a/Jenkinsfile
+++ b/Jenkinsfile
@@ -29,7 +29,7 @@ ci_i386 = "tvmai/ci-i386:v0.52"
// NOTE: docker container provides an extra layer of isolation
docker_run = "tests/scripts/docker_bash.sh"
// timeout in minutes
-max_time = 60
+max_time = 240
// initialize source codes
def init_git() {
diff --git a/tests/scripts/task_tvm_clean.sh b/tests/scripts/task_tvm_clean.sh
index e34ad06..97dd4bf 100755
--- a/tests/scripts/task_tvm_clean.sh
+++ b/tests/scripts/task_tvm_clean.sh
@@ -16,4 +16,4 @@
# specific language governing permissions and limitations
# under the License.
echo "Cleanup data on " $1 " ... "
-cd $1 && rm -rf CMake* && cd -
+cd $1 && rm -rf standalone_crt && rm -rf host_standalone_crt && rm -rf CMake*
&& cd ..
[tvm-vta] branch ci-docker-staging updated: up timeout from 1hr to 4hrs
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch ci-docker-staging
in repository https://gitbox.apache.org/repos/asf/tvm-vta.git
The following commit(s) were added to refs/heads/ci-docker-staging by this push:
new cce4b15 up timeout from 1hr to 4hrs
cce4b15 is described below
commit cce4b159f7b1b470f0ecb2f1b6af2357a014745e
Author: Thierry Moreau
AuthorDate: Thu Apr 15 16:32:44 2021 -0700
up timeout from 1hr to 4hrs
---
Jenkinsfile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Jenkinsfile b/Jenkinsfile
index 8bca45d..33b16f3 100644
--- a/Jenkinsfile
+++ b/Jenkinsfile
@@ -29,7 +29,7 @@ ci_i386 = "tvmai/ci-i386:v0.52"
// NOTE: docker container provides an extra layer of isolation
docker_run = "tests/scripts/docker_bash.sh"
// timeout in minutes
-max_time = 60
+max_time = 240
// initialize source codes
def init_git() {
[tvm-vta] branch ci-docker-staging created (now f11ca65)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch ci-docker-staging in repository https://gitbox.apache.org/repos/asf/tvm-vta.git. at f11ca65 Use TVMArrayCopyFromBytes API to replace VTA internal function VTABufferCPUPtr (#23) No new revisions were added by this update.
[tvm] branch main updated: [Vulkan] Support uniform buffer object for passing many scalar arguments (#7717)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git
The following commit(s) were added to refs/heads/main by this push:
new 5bc1cec [Vulkan] Support uniform buffer object for passing many
scalar arguments (#7717)
5bc1cec is described below
commit 5bc1cec4c4acf0a54889227c1d19a6b65b6803c2
Author: masahi
AuthorDate: Sun Apr 11 10:10:02 2021 +0900
[Vulkan] Support uniform buffer object for passing many scalar arguments
(#7717)
* ubo codegen first cut
* begin runtime change for UBO
* allocate and bind ubo
* query memory type for uniform
* refactor
* do not use float64
* trying an approach similar to push constant
* add more log
* do not delete ubo when not using it
* cumsum and nms test working with ubo
* remove log
* cleaning up
* formatting
* revert BufferArgument change
* refactored codegen
* minor fix
* introduce value kind for ubo
* fix cpplint and revert float64 change
* query push constant size using runtime API
* let vkmap/unmap allocate and delete host_buf
* doc update
* fix typo
Co-authored-by: Masahiro Masuda
---
src/runtime/vulkan/vulkan.cc | 268 +
src/runtime/vulkan/vulkan_common.h | 3 +
src/target/spirv/codegen_spirv.cc | 23 +++-
src/target/spirv/ir_builder.cc | 31 -
src/target/spirv/ir_builder.h | 32 -
5 files changed, 255 insertions(+), 102 deletions(-)
diff --git a/src/runtime/vulkan/vulkan.cc b/src/runtime/vulkan/vulkan.cc
index 5cd4812..c8a0858 100644
--- a/src/runtime/vulkan/vulkan.cc
+++ b/src/runtime/vulkan/vulkan.cc
@@ -91,6 +91,11 @@ struct VulkanBuffer {
VkDeviceMemory memory{VK_NULL_HANDLE};
};
+struct UniformBuffer {
+ VulkanBuffer* vk_buf;
+ void* host_buf;
+};
+
struct VulkanPipeline {
VulkanContext* vctx_{nullptr};
VkShaderModule shader{VK_NULL_HANDLE};
@@ -100,10 +105,105 @@ struct VulkanPipeline {
VkPipelineLayout pipeline_layout{VK_NULL_HANDLE};
VkPipeline pipeline{VK_NULL_HANDLE};
VkDescriptorUpdateTemplateKHR descriptor_update_template{VK_NULL_HANDLE};
+ UniformBuffer ubo;
};
typedef dmlc::ThreadLocalStore VulkanThreadStore;
+uint32_t FindMemoryType(VkDevice logical_device, VkPhysicalDevice phy_device,
VkBuffer buffer,
+VkMemoryPropertyFlags req_prop) {
+ VkMemoryRequirements mem_reqs;
+ vkGetBufferMemoryRequirements(logical_device, buffer, _reqs);
+ uint32_t type_bits = mem_reqs.memoryTypeBits;
+ VkPhysicalDeviceMemoryProperties phy_mem_prop;
+ vkGetPhysicalDeviceMemoryProperties(phy_device, _mem_prop);
+ for (uint32_t i = 0; i < phy_mem_prop.memoryTypeCount; i++) {
+if ((type_bits & 1) == 1 &&
+(phy_mem_prop.memoryTypes[i].propertyFlags & req_prop) == req_prop) {
+ return i;
+}
+type_bits >>= 1;
+ }
+ LOG(FATAL) << "Requested memory type not found";
+ return 0;
+}
+
+VulkanBuffer* CreateBuffer(const VulkanContext& vctx, size_t nbytes,
VkBufferUsageFlags usage) {
+ VkBufferCreateInfo info;
+ info.sType = VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO;
+ info.pNext = nullptr;
+ info.flags = 0;
+ info.size = nbytes;
+ info.queueFamilyIndexCount = 1;
+ info.pQueueFamilyIndices = &(vctx.queue_family_index);
+ info.sharingMode = VK_SHARING_MODE_EXCLUSIVE;
+ info.usage = usage;
+ // create buffer
+ VkBuffer buffer;
+ VULKAN_CALL(vkCreateBuffer(vctx.device, , nullptr, ));
+
+ uint32_t mem_type_index = vctx.compute_mtype_index;
+
+ if (usage & VK_BUFFER_USAGE_UNIFORM_BUFFER_BIT) {
+// Find a memory type that supports UBO
+auto prop = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT;
+mem_type_index = FindMemoryType(vctx.device, vctx.phy_device, buffer,
prop);
+ }
+
+ // bind to memory
+ bool dedicated_allocation = false;
+ VkMemoryRequirements2KHR req2;
+
+ if (vctx.get_buffer_memory_requirements_2_functions) {
+VkBufferMemoryRequirementsInfo2KHR req_info2;
+req_info2.sType = VK_STRUCTURE_TYPE_BUFFER_MEMORY_REQUIREMENTS_INFO_2_KHR;
+req_info2.pNext = 0;
+req_info2.buffer = buffer;
+
+req2.sType = VK_STRUCTURE_TYPE_MEMORY_REQUIREMENTS_2_KHR;
+req2.pNext = 0;
+
+VkMemoryDedicatedRequirementsKHR dedicated_req;
+dedicated_req.sType = VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR;
+dedicated_req.pNext = 0;
+req2.pNext = _req;
+
+
vctx.get_buffer_memory_requirements_2_functions->vkGetBufferMemoryRequirements2KHR(
+vctx.device, _info2, );
+dedicated_allocation =
+dedicated_req.requiresDedicatedAllocation ||
dedicated_req.prefersDedicatedAllocation;
+ }
+
+ VkDeviceMemory memory;
+ if (!dedicated_allocat
[tvm] branch main updated (461d06e -> dec51c5)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 461d06e [TF frontend][bugfix]Avoid making a new node when already has span info (#7789) add dec51c5 Add logical_not shape registration. (#7820) No new revisions were added by this update. Summary of changes: python/tvm/relay/op/_tensor.py | 1 + 1 file changed, 1 insertion(+)
[tvm] branch main updated: [FIX] Make HashCombine stable across platforms (#7801)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git
The following commit(s) were added to refs/heads/main by this push:
new 3ce74f0 [FIX] Make HashCombine stable across platforms (#7801)
3ce74f0 is described below
commit 3ce74f00a5168473578d7e420c3824eed91a1f62
Author: Tristan Konolige
AuthorDate: Tue Apr 6 21:19:34 2021 -0700
[FIX] Make HashCombine stable across platforms (#7801)
* [FIX] Make HashCombine stable across platforms
PR #7605 inadvertatly broke cross platform hashing when when it switched
size_t to uint64_t. This cause a different specialization of HashCombine
to be used. Unfortunately the new specialization used std::hash which is
implementation dependent. I've added tests to make sure this doesn't
happen again.
* fix template specialization issues
---
src/support/utils.h | 19 ---
tests/cpp/support_test.cc | 13 +
2 files changed, 21 insertions(+), 11 deletions(-)
diff --git a/src/support/utils.h b/src/support/utils.h
index 91b9c13..2f55d40 100644
--- a/src/support/utils.h
+++ b/src/support/utils.h
@@ -165,22 +165,19 @@ inline int Execute(std::string cmd, std::string* err_msg)
{
#endif // __hexagon__
/*!
- * \brief Combine two hash values into a single one.
+ * \brief hash an object and combines uint64_t key with previous keys
+ *
+ * This hash function is stable across platforms.
+ *
* \param key The left operand.
* \param value The right operand.
* \return the combined result.
*/
-inline size_t HashCombine(size_t key, size_t value) {
- return key ^ (value + 0x9e3779b9 + (key << 6) + (key >> 2));
-}
-
-/*!
- * \brief hash an object and combines uint64_t key with previous keys
- */
-template
+template ::value, bool> = true>
inline uint64_t HashCombine(uint64_t key, const T& value) {
- std::hash hash_func;
- return key ^ (hash_func(value) + 0x9e3779b9 + (key << 6) + (key >> 2));
+ // XXX: do not use std::hash in this function. This hash must be stable
+ // across different platforms and std::hash is implementation dependent.
+ return key ^ (uint64_t(value) + 0x9e3779b9 + (key << 6) + (key >> 2));
}
} // namespace support
diff --git a/tests/cpp/support_test.cc b/tests/cpp/support_test.cc
index bc9b944..7d523fe 100644
--- a/tests/cpp/support_test.cc
+++ b/tests/cpp/support_test.cc
@@ -21,6 +21,7 @@
#include
#include "../../src/support/hexdump.h"
+#include "../../src/support/utils.h"
namespace tvm {
namespace test {
@@ -43,6 +44,18 @@ TEST(HexDumpTests, Unaligned) {
"\x01\x23\x45\x67\x89\xab\xcd\xef\x01"));
}
+TEST(HashTests, HashStability) {
+ size_t a = 345292;
+ int b = 795620;
+ EXPECT_EQ(::tvm::support::HashCombine(a, b), 2677237020);
+ uint64_t c = 12345;
+ int d = 987654432;
+ EXPECT_EQ(::tvm::support::HashCombine(c, d), 3642871070);
+ size_t e = 1010101;
+ size_t f = 3030303;
+ EXPECT_EQ(::tvm::support::HashCombine(e, f), 2722928432);
+}
+
} // namespace test
} // namespace tvm
[tvm] branch main updated (d31d048 -> 91311b3)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from d31d048 [AutoScheduler] Add task.desc for its function name (#7794) add 91311b3 [Relay]Frontend][Onnx] Remove pop that interferes with nested loops. (#7781) No new revisions were added by this update. Summary of changes: python/tvm/relay/frontend/onnx.py | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-)
[tvm] branch main updated (43c61a2 -> ca0f928)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 43c61a2 add the --net=host cmd line arg to the docker/bash.it script (#7780) add ca0f928 [ONNX] Dynamic Gather (#7787) No new revisions were added by this update. Summary of changes: python/tvm/relay/frontend/onnx.py | 27 - tests/python/frontend/onnx/test_forward.py | 47 ++ 2 files changed, 66 insertions(+), 8 deletions(-)
[tvm] branch main updated (ad775b8 -> a1b4f0e)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from ad775b8 Fix typo in include/tvm/runtime/crt/crt.h and NEWS.md (#7770) add a1b4f0e [Relay]Frontend][Onnx] Add a converter for ATen Nodes (#7747) No new revisions were added by this update. Summary of changes: python/tvm/relay/frontend/onnx.py | 76 +- tests/python/frontend/onnx/test_forward.py | 35 ++ 2 files changed, 109 insertions(+), 2 deletions(-)
[tvm] branch main updated (34deb80 -> e8752c9)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 34deb80 Make Autopad static when available (#7755) add e8752c9 [VTA] Make more explicit error message during sim lib loading failures. (#7761) No new revisions were added by this update. Summary of changes: vta/python/vta/testing/simulator.py | 26 -- 1 file changed, 16 insertions(+), 10 deletions(-)
[tvm] branch main updated (1fe0abc -> 63d8e97)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 1fe0abc [TVMC] Python Scripting Init Files (#7698) add 63d8e97 [µTVM] Rev ci-qemu to 0.02 (Introduce onnx python dependency) (#7728) No new revisions were added by this update. Summary of changes: Jenkinsfile | 2 +- docker/Dockerfile.ci_qemu | 4 ++ docker/install/ubuntu_install_zephyr.sh | 69 + 3 files changed, 7 insertions(+), 68 deletions(-)
[tvm] branch main updated: [Ansor] Add HW param for Vulkan tuning (#7626)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git
The following commit(s) were added to refs/heads/main by this push:
new b2a3c48 [Ansor] Add HW param for Vulkan tuning (#7626)
b2a3c48 is described below
commit b2a3c481ebbb7cfbd5335fb11cd516ae5f348406
Author: masahi
AuthorDate: Fri Mar 12 04:42:47 2021 +0900
[Ansor] Add HW param for Vulkan tuning (#7626)
* add HW param for VK
* query warp size properly
* guard against warp_size < 4 case
Co-authored-by: Masahiro Masuda
---
src/auto_scheduler/search_task.cc | 23 +++
src/runtime/vulkan/vulkan.cc | 25 -
2 files changed, 39 insertions(+), 9 deletions(-)
diff --git a/src/auto_scheduler/search_task.cc
b/src/auto_scheduler/search_task.cc
index 22c2893..f25e581 100755
--- a/src/auto_scheduler/search_task.cc
+++ b/src/auto_scheduler/search_task.cc
@@ -106,6 +106,29 @@ HardwareParams
HardwareParamsNode::GetDefaultHardwareParams(const Target& target
auto target_device = target->GetAttr("device", "");
LOG(FATAL) << "No default hardware parameters for opencl target device:
" << target_device;
}
+ } else if (device_type == kDLVulkan) {
+auto ctx = TVMContext{static_cast(device_type), 0};
+auto device_name = "device_api.vulkan";
+auto func = tvm::runtime::Registry::Get(device_name);
+ICHECK(func != nullptr) << "Cannot find Vulkan device_api in registry";
+auto device_api =
static_cast(((*func)()).operator void*());
+
+tvm::runtime::TVMRetValue ret;
+device_api->GetAttr(ctx,
tvm::runtime::DeviceAttrKind::kMaxSharedMemoryPerBlock, );
+int max_shared_memory_per_block = ret;
+
+int max_local_memory_per_block = INT32_MAX;
+
+device_api->GetAttr(ctx,
tvm::runtime::DeviceAttrKind::kMaxThreadsPerBlock, );
+int max_threads_per_block = ret;
+
+device_api->GetAttr(ctx, tvm::runtime::DeviceAttrKind::kWarpSize, );
+int warp_size = ret;
+
+int max_vthread_extent = std::max(1, warp_size / 4);
+
+return HardwareParams(-1, 16, 64, max_shared_memory_per_block,
max_local_memory_per_block,
+ max_threads_per_block, max_vthread_extent,
warp_size);
} else {
LOG(FATAL) << "No default hardware parameters for target: " << target;
}
diff --git a/src/runtime/vulkan/vulkan.cc b/src/runtime/vulkan/vulkan.cc
index 794f3c5..ff1b82f 100644
--- a/src/runtime/vulkan/vulkan.cc
+++ b/src/runtime/vulkan/vulkan.cc
@@ -367,28 +367,37 @@ void VulkanDeviceAPI::GetAttr(TVMContext ctx,
DeviceAttrKind kind, TVMRetValue*
}
ICHECK_LT(index, context_.size()) << "Invalid device id " << index;
const auto& vctx = context(index);
+ VkPhysicalDeviceProperties phy_prop;
+ vkGetPhysicalDeviceProperties(vctx.phy_device, _prop);
+
switch (kind) {
case kMaxThreadsPerBlock: {
- VkPhysicalDeviceProperties phy_prop;
- vkGetPhysicalDeviceProperties(vctx.phy_device, _prop);
int64_t value = phy_prop.limits.maxComputeWorkGroupInvocations;
*rv = value;
break;
}
case kMaxSharedMemoryPerBlock: {
- VkPhysicalDeviceProperties phy_prop;
- vkGetPhysicalDeviceProperties(vctx.phy_device, _prop);
int64_t value = phy_prop.limits.maxComputeSharedMemorySize;
*rv = value;
break;
}
case kWarpSize: {
- *rv = 1;
+ VkPhysicalDeviceSubgroupProperties subgroup_prop;
+ subgroup_prop.sType =
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES;
+ subgroup_prop.pNext = NULL;
+
+ VkPhysicalDeviceProperties2 phy_prop2;
+ phy_prop2.sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROPERTIES_2;
+ phy_prop2.pNext = _prop;
+
+ vkGetPhysicalDeviceProperties2(vctx.phy_device, _prop2);
+ int64_t subgroup_size = subgroup_prop.subgroupSize;
+ ICHECK(subgroup_size >= 1);
+
+ *rv = subgroup_size;
break;
}
case kComputeVersion: {
- VkPhysicalDeviceProperties phy_prop;
- vkGetPhysicalDeviceProperties(vctx.phy_device, _prop);
int64_t value = phy_prop.apiVersion;
std::ostringstream os;
os << VK_VERSION_MAJOR(value) << "." << VK_VERSION_MINOR(value) << "."
@@ -405,8 +414,6 @@ void VulkanDeviceAPI::GetAttr(TVMContext ctx,
DeviceAttrKind kind, TVMRetValue*
case kExist:
break;
case kMaxThreadDimensions: {
- VkPhysicalDeviceProperties phy_prop;
- vkGetPhysicalDeviceProperties(vctx.phy_device, _prop);
int64_t dims[3];
dims[0] = phy_prop.limits.maxComputeWorkGroupSize[0];
dims[1] = phy_prop.limits.maxComputeWorkGroupSize[1];
[tvm] branch main updated (8d1f5b2 -> 717c5e0)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 8d1f5b2 [Relay] Fix relay op strategy for cuda dense int8 (#7586) add 717c5e0 Add logging to diagnose flaky ci-qemu test (#7610) No new revisions were added by this update. Summary of changes: tests/scripts/task_python_microtvm.sh | 1 + 1 file changed, 1 insertion(+)
[tvm] branch main updated: [Autoscheduler][VM] Autoscheduler layout rewrite pass to VM (#7516)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git
The following commit(s) were added to refs/heads/main by this push:
new a1d43c1 [Autoscheduler][VM] Autoscheduler layout rewrite pass to VM
(#7516)
a1d43c1 is described below
commit a1d43c15ac6382831370c6de141bf80888761e70
Author: Thierry Moreau
AuthorDate: Mon Mar 1 17:31:57 2021 -0800
[Autoscheduler][VM] Autoscheduler layout rewrite pass to VM (#7516)
* fix type inference for conv2d
* fix
* adding the autoscheduler layout rewrite pass to VM compiler passes
* revert edits applied in other PR
* minor fix
* fix
* formatting fix
* lint
---
src/relay/backend/vm/compiler.cc | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/src/relay/backend/vm/compiler.cc b/src/relay/backend/vm/compiler.cc
index 7697b59..0718191 100644
--- a/src/relay/backend/vm/compiler.cc
+++ b/src/relay/backend/vm/compiler.cc
@@ -1066,6 +1066,23 @@ IRModule VMCompiler::OptimizeModule(IRModule mod, const
TargetsMap& targets,
}
pass_seqs.push_back(transform::FuseOps());
+ // Do layout rewrite for auto-scheduler.
+ transform::PassContext pass_ctx = PassContext::Current();
+ if (backend::IsAutoSchedulerEnabled() && targets.size() == 1) {
+const auto& target = (*targets.begin()).second;
+Pass major_pass = transform::AutoSchedulerLayoutRewrite();
+bool enable_layout_rewrite_targets =
+target->kind->device_type == kDLCPU ||
target->GetAttr("device", "") == "mali";
+if (enable_layout_rewrite_targets &&
pass_ctx.PassEnabled(major_pass->Info())) {
+ With tctx(target);
+ pass_seqs.push_back(major_pass);
+ // Defuse ops to fold constants, then fuse them again
+ pass_seqs.push_back(transform::DefuseOps());
+ pass_seqs.push_back(transform::FoldConstant());
+ pass_seqs.push_back(transform::FuseOps());
+}
+ }
+
pass_seqs.push_back(transform::ToANormalForm());
pass_seqs.push_back(transform::InferType());
pass_seqs.push_back(transform::LambdaLift());
@@ -1082,7 +1099,6 @@ IRModule VMCompiler::OptimizeModule(IRModule mod, const
TargetsMap& targets,
pass_seqs.push_back(transform::InferType());
transform::Sequential seq(pass_seqs);
- transform::PassContext pass_ctx = PassContext::Current();
tvm::With ctx(pass_ctx);
if (targets.size() == 1) {
const auto& it = targets.begin();
[tvm] branch main updated: Don't run non-tvm_op GraphRuntime nodes in Debug Runtime over RPC. (#7512)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git
The following commit(s) were added to refs/heads/main by this push:
new f6d0fee Don't run non-tvm_op GraphRuntime nodes in Debug Runtime over
RPC. (#7512)
f6d0fee is described below
commit f6d0feef52f7b4c037150f405c37e693b4884f7f
Author: Andrew Reusch
AuthorDate: Fri Feb 26 17:32:43 2021 -0800
Don't run non-tvm_op GraphRuntime nodes in Debug Runtime over RPC. (#7512)
* Don't run non-tvm_op GraphRuntime nodes in Debug Runtime over RPC.
* These are filtered out in SetupOpExecs for normal debug runtime
operation.
* retrigger CI
* retrigger CI
* address tkonolige comment
---
src/runtime/graph/debug/graph_runtime_debug.cc | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/runtime/graph/debug/graph_runtime_debug.cc
b/src/runtime/graph/debug/graph_runtime_debug.cc
index 0b8f39d..93bdd06 100644
--- a/src/runtime/graph/debug/graph_runtime_debug.cc
+++ b/src/runtime/graph/debug/graph_runtime_debug.cc
@@ -110,6 +110,19 @@ class GraphRuntimeDebug : public GraphRuntime {
}
double RunOpRPC(int index, int number, int repeat, int min_repeat_ms) {
+// Right now we expect either "tvm_op" for nodes which run PackedFunc or
"null" for nodes which
+// represent inputs/parameters to the graph. Other types may be supported
in the future, but
+// consideration would be needed as to how to do that over RPC before we
support it here.
+if (nodes_[index].op_type != "tvm_op") {
+ CHECK_EQ(nodes_[index].op_type, "null")
+ << "Don't know how to run op type " << nodes_[index].op_type
+ << " remotely over RPC right now";
+
+ // NOTE: GraphRuntimeDebug expects graph nodes to have an "op" attribute
of "tvm_op" or "null"
+ // and "null" is a placeholder node for a parameter or input.
+ return 0;
+}
+
const TVMContext& ctx = data_entry_[entry_id(index, 0)]->ctx;
TVMOpParam param = nodes_[index].param;
std::string name = param.func_name;
[tvm] branch main updated (74ca8f0 -> 0758337)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 74ca8f0 [CI] Move ci-cpu to use llvm-11 (#7541) add 0758337 Add create_local_debug_runtime to micro exports (#7528) No new revisions were added by this update. Summary of changes: python/tvm/micro/__init__.py | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-)
[tvm] branch main updated: Introduce module_loader to AutoTVM. (#7337)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a commit to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git The following commit(s) were added to refs/heads/main by this push: new b111695 Introduce module_loader to AutoTVM. (#7337) b111695 is described below commit b1116954f532d869a7ce8d9eb24745f368b66e59 Author: Andrew Reusch AuthorDate: Thu Feb 25 10:27:06 2021 -0800 Introduce module_loader to AutoTVM. (#7337) * Introduce code_loader to AutoTVM. * Prepares for autotuning with microTVM, and provides extension hook for VTA. * add vta hook * git-black * pylint * Add missing import * Fix import problem * add missing import * rename code_loader to module_loader * rename remote_kw to remote_kwargs * black format --- python/tvm/autotvm/measure/__init__.py| 8 +- python/tvm/autotvm/measure/measure_methods.py | 138 +- vta/python/vta/__init__.py| 1 + vta/python/vta/autotvm.py | 52 ++ vta/tutorials/autotvm/tune_relay_vta.py | 1 + 5 files changed, 150 insertions(+), 50 deletions(-) diff --git a/python/tvm/autotvm/measure/__init__.py b/python/tvm/autotvm/measure/__init__.py index 0c32ae0..c4c0dc9 100644 --- a/python/tvm/autotvm/measure/__init__.py +++ b/python/tvm/autotvm/measure/__init__.py @@ -23,6 +23,12 @@ from .measure import ( measure_option, create_measure_batch, ) -from .measure_methods import LocalBuilder, LocalRunner, RPCRunner, request_remote +from .measure_methods import ( +LocalBuilder, +LocalRunner, +RPCRunner, +default_module_loader, +request_remote, +) from .executor import Executor from .local_executor import LocalExecutor diff --git a/python/tvm/autotvm/measure/measure_methods.py b/python/tvm/autotvm/measure/measure_methods.py index ffe4b97..62fd811 100644 --- a/python/tvm/autotvm/measure/measure_methods.py +++ b/python/tvm/autotvm/measure/measure_methods.py @@ -22,11 +22,13 @@ These functions are responsible for building the tvm module, uploading it to remote devices, recording the running time costs, and checking the correctness of the output. """ +import contextlib import logging import shutil import os import threading import time +import typing from random import getrandbits from collections import namedtuple import tempfile @@ -199,6 +201,9 @@ class RPCRunner(Runner): its actual latency during end-to-end inference. To make this option effective, the argument `number` should also be set to 1. This is only has effect on CPU task. +module_loader : ModuleLoader +If given, a context manager that loads the module to be timed into the remote runtime. +If not given, default_module_loader is used. """ def __init__( @@ -214,6 +219,7 @@ class RPCRunner(Runner): min_repeat_ms=0, cooldown_interval=0.1, enable_cpu_cache_flush=False, +module_loader=None, ): super(RPCRunner, self).__init__(timeout, n_parallel) @@ -229,6 +235,7 @@ class RPCRunner(Runner): self.enable_cpu_cache_flush = enable_cpu_cache_flush self.cooldown_interval = cooldown_interval +self.module_loader = module_loader self.executor = LocalExecutor(timeout=timeout * (self.n_parallel + 1)) @@ -280,6 +287,11 @@ class RPCRunner(Runner): for measure_inp, build_res in zip( measure_inputs[i : i + self.n_parallel], build_results[i : i + self.n_parallel] ): +module_loader = ( +self.module_loader +if self.module_loader is not None +else default_module_loader() +) ret = self.executor.submit( run_through_rpc, measure_inp, @@ -290,6 +302,7 @@ class RPCRunner(Runner): self.cooldown_interval, remote_args, self.enable_cpu_cache_flush, +module_loader, ) futures.append(ret) @@ -352,6 +365,7 @@ class LocalRunner(RPCRunner): min_repeat_ms=0, cooldown_interval=0.1, enable_cpu_cache_flush=False, +module_loader=None, ): super(LocalRunner, self).__init__( "", @@ -365,6 +379,7 @@ class LocalRunner(RPCRunner): min_repeat_ms=min_repeat_ms, cooldown_interval=cooldown_interval, enable_cpu_cache_flush=enable_cpu_cache_flush, +module_loader=module_loader, ) self.tracker = None self.server = None @@ -473,6 +488,11 @@ class _WrappedBuildFunc: return BuildResult(filename, arg_info, None, time.time() -
[tvm] branch main updated (d94cbbb -> 0ba3741)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a change to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git.
from d94cbbb [Frontend]Make onnx gemm tensor C optional (#7489)
add 0ba3741 [CRT] Create C-runtime-style metadata module for llvm builds
(#7398)
No new revisions were added by this update.
Summary of changes:
apps/bundle_deploy/Makefile| 19 ++-
apps/bundle_deploy/build_model.py | 25 +++-
python/tvm/driver/build_module.py | 21 ++--
python/tvm/micro/compiler.py | 6 +-
src/target/llvm/codegen_cpu.cc | 85 +++--
src/target/llvm/codegen_cpu.h | 6 +
src/target/llvm/llvm_module.cc | 53
.../llvm_module.h} | 27 ++--
src/target/metadata_module.cc | 136 +
.../{llvm/codegen_params.h => metadata_module.h} | 27 ++--
src/target/source/codegen_source_base.h| 5 +-
src/target/source/source_module.cc | 88 +++--
.../codegen_params.h => source/source_module.h}| 27 ++--
tests/python/unittest/test_crt.py | 33 -
tests/python/unittest/test_link_params.py | 30 +++--
tests/python/unittest/test_target_codegen_llvm.py | 28 +
16 files changed, 400 insertions(+), 216 deletions(-)
copy src/target/{func_registry_generator.h => llvm/llvm_module.h} (65%)
create mode 100644 src/target/metadata_module.cc
copy src/target/{llvm/codegen_params.h => metadata_module.h} (61%)
copy src/target/{llvm/codegen_params.h => source/source_module.h} (60%)
[tvm] branch ci-docker-staging updated (db93cb8 -> 6a77cdd)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a change to branch ci-docker-staging
in repository https://gitbox.apache.org/repos/asf/tvm.git.
from db93cb8 retrigger CI
add 2b8d113 [TVMC] Allow manual shape specification in tvmc (#7366)
add 0716c2a [AutoScheduler] Add sampling to dispatcher (#7376)
add 2999d03 [ONNX] Add CumSum operator to ONNX frontend (#7391)
add 68b7e71 [Relay][Topi][CPU] Dense with weight transform (#7404)
add 3863e09 [FIX,CMAKE] Only set Clang flags for C++ files (#7424)
add 9175c6d TRT Dynamic Reshape Fix (#7412)
add 12c6b70 Simplify full broadcast (#7423)
add b7808fb [Arith] Fix iter_affine_map with non-const extent (#7437)
add d05d75d Stop running some python testsuites twice (#7430)
add 6b58321 [BYOC][TRT] Fix small bug preventing TRT runtime compilation
for versions < 6 (#7372)
add 8b9005f Make the TVM targets list available in Python (#7427)
add c52c176 Replace type punning with memcpy. (#7415)
add 33829b3 Fix double compile of runtime sources for TRT, ACL (#7436)
add d5851dd [TIR][Printer] Fix SelectNode TIRTextPrinter bracket mismatch
(#7405)
add c7c54de Update tags with minor fix (#7448)
add d769727 Add ROCm docker (#7422)
add e426c87 [AutoScheduler] Fix distill record (#7439)
add b36bdf6 [Relay][Op][Bug] Fix missing return in scatter_nd cuda
strategy (#7447)
add a1260cc Make keras reshape less restrictive (#7446)
add f9ff088 Merge remote-tracking branch 'origin/main' into junit-enable
add 6a77cdd prefix junit results with FFI type
No new revisions were added by this update.
Summary of changes:
CMakeLists.txt | 4 +-
cmake/modules/ClangFlags.cmake | 19 ++--
cmake/modules/contrib/ArmComputeLib.cmake | 4 +-
cmake/modules/contrib/TensorRT.cmake | 4 +-
.../{Dockerfile.ci_wasm => Dockerfile.demo_rocm} | 20 +---
docker/bash.sh | 16 ++-
docker/install/ubuntu_install_rocm.sh | 6 +-
docker/with_the_same_user | 6 ++
include/tvm/relay/attrs/transform.h| 4 +
include/tvm/relay/dataflow_pattern.h | 2 +
include/tvm/target/target_kind.h | 5 +
python/tvm/auto_scheduler/__init__.py | 2 +-
python/tvm/auto_scheduler/dispatcher.py| 93 +++-
python/tvm/auto_scheduler/measure_record.py| 52 +
python/tvm/driver/tvmc/autotuner.py| 9 +-
python/tvm/driver/tvmc/common.py | 39 +++
python/tvm/driver/tvmc/compiler.py | 16 ++-
python/tvm/driver/tvmc/frontends.py| 47
python/tvm/relay/frontend/keras.py | 31 ++
python/tvm/relay/frontend/onnx.py | 25 -
python/tvm/relay/op/_transform.py | 2 +-
python/tvm/relay/op/contrib/tensorrt.py| 13 ++-
python/tvm/relay/op/nn/_nn.py | 30 ++
python/tvm/relay/op/nn/nn.py | 33 ++
python/tvm/relay/op/strategy/cuda.py | 1 +
python/tvm/relay/op/strategy/generic.py| 15 ++-
python/tvm/relay/op/strategy/x86.py| 28 +++--
python/tvm/relay/op/transform.py | 12 ++-
python/tvm/target/target.py| 5 +
python/tvm/topi/cuda/scan.py | 10 +-
python/tvm/topi/cumsum.py | 21 +++-
python/tvm/topi/nn/dense.py| 70
python/tvm/topi/x86/__init__.py| 1 +
python/tvm/topi/x86/dense.py | 120 +++--
python/tvm/topi/x86/dense_alter_op.py | 68
src/arith/iter_affine_map.cc | 36 ---
src/printer/tir_text_printer.cc| 2 +-
src/relay/ir/dataflow_matcher.cc | 8 +-
src/relay/ir/dataflow_pattern.cc | 1 +
src/relay/op/make_op.h | 6 ++
src/relay/op/nn/nn.cc | 27 +
src/relay/op/nn/nn.h | 25 +
src/relay/op/tensor/transform.cc | 3 +-
src/relay/op/tensor/unary.cc | 6 +-
src/relay/transforms/fold_constant.cc | 5 -
src/relay/transforms/simplify_expr.cc | 111 ---
src/runtime/contrib/tensorrt/tensorrt_ops.cc | 2 +-
src/runtime/crt/common/ndarray.c | 14 +--
src/runtime/crt/graph_runtime/graph_runtime.c | 10 +-
src/target/tag.cc | 13 +--
src/target/target_kind.cc | 9 ++
tests/cpp/target_t
[tvm] branch main updated: [BYOC][Verilator] Refactor Verilator runtime (#7406)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git
The following commit(s) were added to refs/heads/main by this push:
new fc48514 [BYOC][Verilator] Refactor Verilator runtime (#7406)
fc48514 is described below
commit fc48514f1d8ccffcebd12007cb6c602506975703
Author: Luis Vega
AuthorDate: Mon Feb 15 20:02:10 2021 -0800
[BYOC][Verilator] Refactor Verilator runtime (#7406)
* new experiment
* save
* refactor
* refactor library
* add profiler
* refactor
* refactor
* add docs
* update comment
* add deallocator
---
src/relay/backend/contrib/verilator/codegen.cc | 56 +++---
src/runtime/contrib/verilator/verilator_device.h | 39 +++-
src/runtime/contrib/verilator/verilator_runtime.cc | 197 +++--
src/runtime/contrib/verilator/verilator_runtime.h | 138 +++
.../contrib/test_verilator/infrastructure.py | 6 +-
5 files changed, 307 insertions(+), 129 deletions(-)
diff --git a/src/relay/backend/contrib/verilator/codegen.cc
b/src/relay/backend/contrib/verilator/codegen.cc
index 2f61ae5..b206288 100644
--- a/src/relay/backend/contrib/verilator/codegen.cc
+++ b/src/relay/backend/contrib/verilator/codegen.cc
@@ -34,6 +34,7 @@
#include
#include "../../../../runtime/contrib/json/json_node.h"
+#include "../../../../runtime/contrib/verilator/verilator_runtime.h"
#include "../../utils.h"
#include "../codegen_json/codegen_json.h"
@@ -75,29 +76,34 @@ class VerilatorJSONSerializer : public
backend::contrib::JSONSerializer {
}
};
-/*! \brief Attributes to store the compiler options for Verilator */
-struct VerilatorCompilerConfigNode : public
tvm::AttrsNode {
- String lib;
-
- TVM_DECLARE_ATTRS(VerilatorCompilerConfigNode,
"ext.attrs.VerilatorCompilerConfigNode") {
-TVM_ATTR_FIELD(lib).set_default("libverilator.so");
+/*! \brief Attributes to store options for Verilator */
+struct VerilatorOptionsNode : public tvm::AttrsNode {
+ String lib_path;
+ int reset_cycles;
+ bool profiler_enable;
+ int profiler_cycle_counter_id;
+
+ TVM_DECLARE_ATTRS(VerilatorOptionsNode, "ext.attrs.VerilatorOptionsNode") {
+TVM_ATTR_FIELD(lib_path).describe("the design library
path").set_default("libverilator.so");
+TVM_ATTR_FIELD(reset_cycles).describe("the number of reset
cycles").set_default(1);
+TVM_ATTR_FIELD(profiler_enable).describe("enable
profiler").set_default(false);
+TVM_ATTR_FIELD(profiler_cycle_counter_id).describe("profiler cycle counter
id").set_default(0);
}
};
-class VerilatorCompilerConfig : public Attrs {
+class VerilatorOptions : public Attrs {
public:
- TVM_DEFINE_NOTNULLABLE_OBJECT_REF_METHODS(VerilatorCompilerConfig, Attrs,
-VerilatorCompilerConfigNode);
+ TVM_DEFINE_NOTNULLABLE_OBJECT_REF_METHODS(VerilatorOptions, Attrs,
VerilatorOptionsNode);
};
-TVM_REGISTER_NODE_TYPE(VerilatorCompilerConfigNode);
-TVM_REGISTER_PASS_CONFIG_OPTION("relay.ext.verilator.options",
VerilatorCompilerConfig);
+TVM_REGISTER_NODE_TYPE(VerilatorOptionsNode);
+TVM_REGISTER_PASS_CONFIG_OPTION("relay.ext.verilator.options",
VerilatorOptions);
/*!
- * \brief The external compiler/codegen tool. It takes a Relay
expression/module and
- * compile it into a runtime module.
+ * \brief The Verilator codegen tool. It takes a Relay expression/module and
+ * compile it into a Verilator runtime module.
*/
-runtime::Module VerilatorCompiler(const ObjectRef& ref) {
+runtime::Module VerilatorBackend(const ObjectRef& ref) {
CHECK(ref->IsInstance());
auto func = Downcast(ref);
auto func_name = GetExtSymbol(func);
@@ -106,22 +112,28 @@ runtime::Module VerilatorCompiler(const ObjectRef& ref) {
std::string graph_json = serializer.GetJSON();
auto params = serializer.GetParams();
+ // Create runtime object
+ auto n = make_object(func_name,
graph_json, params);
+
// Get Verilator compiler options
auto ctx = transform::PassContext::Current();
- auto cfg =
ctx->GetConfig("relay.ext.verilator.options");
+ auto cfg = ctx->GetConfig("relay.ext.verilator.options");
if (!cfg.defined()) {
-cfg = AttrsWithDefaultValues();
+cfg = AttrsWithDefaultValues();
}
- auto lib_name = cfg.value()->lib;
+ n->SetLibrary(cfg.value()->lib_path);
+ n->SetResetCycles(cfg.value()->reset_cycles);
+
+ if (cfg.value()->profiler_enable) {
+n->EnableProfiler();
+n->SetProfilerCycleCounterId(cfg.value()->profiler_cycle_counter_id);
+ }
- const auto* pf = runtime::Registry::Get("runtime.verilator_runtime_create");
- CHECK(pf != nullptr) << "Can
[tvm] branch main updated: [µTVM] Print .elf statistics for a model runtime built with Zephyr (#7449)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git
The following commit(s) were added to refs/heads/main by this push:
new 32c4402 [µTVM] Print .elf statistics for a model runtime built with
Zephyr (#7449)
32c4402 is described below
commit 32c44025483b9aea7732cdc80e85e8e973c602ab
Author: Gustavo Romero
AuthorDate: Mon Feb 15 15:22:00 2021 -0300
[µTVM] Print .elf statistics for a model runtime built with Zephyr (#7449)
* [µTVM] Print .elf statistics for a model runtime built with Zephyr
Currently there isn't any statistics about the used resources by a model
runtime built with Zephyr, making it difficult to have any idea about, for
instance, the amount of memory taken by the operations necessary to run the
model.
Since Zephyr's SDK already exposes the statistics about various memory
regions on linking by passing '--print-memory-usage' to the linker, it's
possible to use it to have an idea about the amount of memory used by the
model and how much memory is left on the device.
That commit adds a simple method to extract the memory region information
out of the build output and then uses it to show memory usage statistics
for various memory regions when Zephyr finishes building the image to be
flashed to the target device.
Signed-off-by: Gustavo Romero
* v2: Fixes accordingly to Andrew review
- Catch StopIteration in case of a weird output or no additional lines
after the last memory region
- Use of _LOG.info() instead of plain print() for better control over
the output by the main script
- Set log level in micro_tflite.py script as an example on how to get
the new memory usage statistics and also because currently that's the
main script used to test microTVM + Zephyr's SDK
- Improve statistics header
Signed-off-by: Gustavo Romero
* Fix build
It seems build system is using Python < 3.7, so 'text' argument
is not present as an alias for 'universal_newlines'. To satisfy
it use old 'universal_newlines' argument which is available prior
to Python 3.7.
* Fix build
Avoid exception anti-pattern when catching StopIteration
* Retrigger CI
---
python/tvm/micro/contrib/zephyr.py | 25 +++--
tutorials/micro/micro_tflite.py| 6 ++
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/python/tvm/micro/contrib/zephyr.py
b/python/tvm/micro/contrib/zephyr.py
index ed1c986..29bb5ec 100644
--- a/python/tvm/micro/contrib/zephyr.py
+++ b/python/tvm/micro/contrib/zephyr.py
@@ -55,7 +55,7 @@ class SubprocessEnv(object):
for k, v in self.default_overrides.items():
env[k] = v
-return subprocess.check_output(cmd, env=env, **kw)
+return subprocess.check_output(cmd, env=env, **kw,
universal_newlines=True)
class ProjectNotFoundError(Exception):
@@ -204,6 +204,25 @@ class ZephyrCompiler(tvm.micro.Compiler):
)
return tvm.micro.MicroLibrary(build_dir, [f"lib{project_name}.a"])
+def _print_make_statistics(self, output):
+output = output.splitlines()
+lines = iter(output)
+for line in lines:
+if line.startswith("Memory region"):
+# print statistics header
+_LOG.info(line)
+_LOG.info("- --
-")
+line = next(lines)
+# while there is a region print it
+try:
+while ":" in line:
+_LOG.info(line)
+line = next(lines)
+else:
+break
+except StopIteration:
+pass
+
def binary(self, output, objects, options=None, link_main=True,
main_options=None):
assert link_main, "Must pass link_main=True"
assert self._project_dir is not None, "Must supply project_dir= to
build binaries"
@@ -224,7 +243,9 @@ class ZephyrCompiler(tvm.micro.Compiler):
cmake_args.append(f'-DTVM_LIBS={";".join(copied_libs)}')
self._subprocess_env.run(cmake_args, cwd=output)
-self._subprocess_env.run(["make"], cwd=output)
+make_output = self._subprocess_env.run(["make"], cwd=output)
+
+self._print_make_statistics(make_output)
return tvm.micro.MicroBinary(
output,
diff --git a/tutorials/micro/micro_tflite.py b/tutorials/micro/micro_tflite.py
index 673985e..6ad0da5 100644
--- a/tutorials/micro/micro_tflite.py
+++ b/tutorials/micro/micro_tflite.py
@@ -122,6 +122,8 @@ model with Relay.
import os
import numpy as np
+import logging
+
import tvm
im
[tvm] branch main updated: [ONNX] Make the ONNX Importer More Static (#7429)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git
The following commit(s) were added to refs/heads/main by this push:
new 4e211a7 [ONNX] Make the ONNX Importer More Static (#7429)
4e211a7 is described below
commit 4e211a735221a9b9d188422025e2d464e37b3c96
Author: Matthew Brookhart
AuthorDate: Fri Feb 12 21:14:56 2021 -0700
[ONNX] Make the ONNX Importer More Static (#7429)
* Construct static Ops if inputs are Constant
* Expose FoldConstant as a function in addition to the pass
* refactor onnx importer to do more static imports by constant folding
fix pylint
* fix test regressions
* fix style, two bugs
* pipe freeze_params through sub_graphs when importing loops and control
flow
---
python/tvm/relay/frontend/common.py | 6 +
python/tvm/relay/frontend/onnx.py | 198 +-
python/tvm/relay/op/image/image.py| 4 +-
python/tvm/relay/op/nn/nn.py | 16 ++-
python/tvm/relay/op/tensor.py | 6 +-
python/tvm/relay/op/transform.py | 18 ++-
python/tvm/relay/transform/transform.py | 17 +++
src/relay/transforms/fold_constant.cc | 2 +
tests/python/relay/test_op_grad_level3.py | 2 +-
9 files changed, 180 insertions(+), 89 deletions(-)
diff --git a/python/tvm/relay/frontend/common.py
b/python/tvm/relay/frontend/common.py
index 6323c63..2db420a 100644
--- a/python/tvm/relay/frontend/common.py
+++ b/python/tvm/relay/frontend/common.py
@@ -491,6 +491,12 @@ def infer_type(node, mod=None):
return ret
+def fold_constant(node, mod=None):
+if mod is None:
+mod = IRModule.from_expr(node)
+return _transform.FoldConstantExpr(node, mod)
+
+
def infer_channels(inputs, transpose=False):
"""A hack for getting 'channels' or 'units' since caffe2 does not provide
these attributes. We check the shape of weights provided to get the number.
diff --git a/python/tvm/relay/frontend/onnx.py
b/python/tvm/relay/frontend/onnx.py
index c9140d7..fb3d1c9 100644
--- a/python/tvm/relay/frontend/onnx.py
+++ b/python/tvm/relay/frontend/onnx.py
@@ -34,7 +34,7 @@ from .. import loops as _loops
from .. import ty as _ty
from .common import AttrCvt, Renamer
-from .common import get_relay_op, new_var, infer_shape, infer_channels,
infer_value
+from .common import get_relay_op, new_var, infer_shape, infer_channels,
infer_value, fold_constant
from .common import infer_type, get_name
@@ -364,7 +364,7 @@ def autopad(data, strides, kernel_shape, dilations, ndim,
pad_type="constant", d
),
dtype="int64",
)
-shape = _op.strided_slice(_op.shape_of(data, dtype="int64"), [2], [ndim])
+shape = _op.strided_slice(shape_of(data, dtype="int64"), [2], [ndim])
# get input shape
# set up integer constants
@@ -545,9 +545,9 @@ class MatMul(OnnxOpConverter):
def _impl_v1(cls, inputs, attr, params):
assert len(inputs) == 2, "MatMul op take 2 inputs, {}
given".format(len(inputs))
# Need to check input shape as batch matmul must be supported.
-a_shape = _op.shape_of(inputs[0])
+a_shape = shape_of(inputs[0])
a_rank = infer_shape(a_shape)[0]
-b_shape = _op.shape_of(inputs[1])
+b_shape = shape_of(inputs[1])
b_rank = infer_shape(b_shape)[0]
# When performing a batch matmul, we need to properly handle N-dim
shapes.
if a_rank > 2 or b_rank > 2:
@@ -555,9 +555,13 @@ class MatMul(OnnxOpConverter):
def flatten_to_3d(x, x_shape):
ndims = infer_shape(x_shape)[0]
newshape = _op.concatenate(
-[_expr.const([-1]), _op.strided_slice(x_shape, [ndims -
2], [ndims])], 0
+[
+_expr.const([-1],
dtype=infer_type(x_shape).checked_type.dtype),
+_op.strided_slice(x_shape, [ndims - 2], [ndims]),
+],
+0,
)
-out = _op.reshape(x, newshape)
+out = _op.reshape(x, fold_constant(newshape))
return out
# Convert a and b into 3 dimensional tensors.
@@ -598,7 +602,7 @@ class MatMul(OnnxOpConverter):
],
0,
)
-return _op.reshape(output, final_shape)
+return _op.reshape(output, fold_constant(final_shape))
# Otherwise a simple dense op will get the job done.
input_1_t = _op.transpose(inputs[1], axes=(1, 0))
return _op.nn.dense(inputs[0], input_1_t)
@@ -646,7 +650,7 @@ class MaxUnpool(OnnxOpConverter):
multiplier = _op.concatenate(
[_expr.const([1, 1], dtype="int64"), _expr.const(list(strides),
dtype=&qu
[tvm] branch main updated (a1260cc -> b8a8340)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from a1260cc Make keras reshape less restrictive (#7446) add b8a8340 [µTVM] Use standalone_crt build tree for all µTVM builds (#7333) No new revisions were added by this update. Summary of changes: cmake/modules/StandaloneCrt.cmake | 8 +- python/tvm/micro/__init__.py | 4 +- python/tvm/micro/build.py | 174 -- python/tvm/micro/compiler.py | 5 +- tests/micro/qemu/test_zephyr.py | 3 +- tests/python/unittest/test_crt.py | 13 +-- tests/python/unittest/test_link_params.py | 13 +-- tests/scripts/task_ci_setup.sh| 5 + tutorials/micro/micro_tflite.py | 13 +-- 9 files changed, 148 insertions(+), 90 deletions(-)
[tvm] branch main updated (8b9005f -> c52c176)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 8b9005f Make the TVM targets list available in Python (#7427) add c52c176 Replace type punning with memcpy. (#7415) No new revisions were added by this update. Summary of changes: src/runtime/crt/common/ndarray.c | 14 +++--- src/runtime/crt/graph_runtime/graph_runtime.c | 10 +- 2 files changed, 12 insertions(+), 12 deletions(-)
[tvm] 01/01: Enable JUnit parsing for Python tests
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a commit to branch ci-docker-staging
in repository https://gitbox.apache.org/repos/asf/tvm.git
commit 27bed740784cf6b92f12af76085725a4920e7db1
Author: Andrew Reusch
AuthorDate: Mon Feb 8 20:08:23 2021 -0800
Enable JUnit parsing for Python tests
---
Jenkinsfile | 8
1 file changed, 8 insertions(+)
diff --git a/Jenkinsfile b/Jenkinsfile
index 6bf6dcf..1232028 100644
--- a/Jenkinsfile
+++ b/Jenkinsfile
@@ -188,6 +188,7 @@ stage('Build') {
sh "${docker_run} ${ci_cpu} ./tests/scripts/task_python_vta_tsim.sh"
// sh "${docker_run} ${ci_cpu} ./tests/scripts/task_golang.sh"
sh "${docker_run} ${ci_cpu} ./tests/scripts/task_rust.sh"
+ junit "./build/pytest-results/*.xml"
}
}
}
@@ -234,6 +235,7 @@ stage('Build') {
timeout(time: max_time, unit: 'MINUTES') {
sh "${docker_run} ${ci_qemu} ./tests/scripts/task_ci_setup.sh"
sh "${docker_run} ${ci_qemu} ./tests/scripts/task_python_microtvm.sh"
+ junit "./build/pytest-results/*.xml"
}
}
}
@@ -251,6 +253,7 @@ stage('Unit Test') {
sh "${docker_run} ${ci_gpu} ./tests/scripts/task_sphinx_precheck.sh"
sh "${docker_run} ${ci_gpu}
./tests/scripts/task_python_unittest_gpuonly.sh"
sh "${docker_run} ${ci_gpu}
./tests/scripts/task_python_integration_gpuonly.sh"
+ junit "./build/pytest-results/*.xml"
}
}
}
@@ -265,6 +268,7 @@ stage('Unit Test') {
sh "${docker_run} ${ci_i386} ./tests/scripts/task_python_unittest.sh"
sh "${docker_run} ${ci_i386}
./tests/scripts/task_python_integration.sh"
sh "${docker_run} ${ci_i386} ./tests/scripts/task_python_vta_fsim.sh"
+ junit "./build/pytest-results/*.xml"
}
}
}
@@ -277,6 +281,7 @@ stage('Unit Test') {
timeout(time: max_time, unit: 'MINUTES') {
sh "${docker_run} ${ci_arm} ./tests/scripts/task_ci_setup.sh"
sh "${docker_run} ${ci_arm} ./tests/scripts/task_python_unittest.sh"
+ junit "./build/pytest-results/*.xml"
// sh "${docker_run} ${ci_arm}
./tests/scripts/task_python_integration.sh"
}
}
@@ -305,6 +310,7 @@ stage('Integration Test') {
timeout(time: max_time, unit: 'MINUTES') {
sh "${docker_run} ${ci_gpu} ./tests/scripts/task_ci_setup.sh"
sh "${docker_run} ${ci_gpu} ./tests/scripts/task_python_topi.sh"
+ junit "./build/pytest-results/*.xml"
}
}
}
@@ -317,6 +323,7 @@ stage('Integration Test') {
timeout(time: max_time, unit: 'MINUTES') {
sh "${docker_run} ${ci_gpu} ./tests/scripts/task_ci_setup.sh"
sh "${docker_run} ${ci_gpu} ./tests/scripts/task_python_frontend.sh"
+ junit "./build/pytest-results/*.xml"
}
}
}
@@ -329,6 +336,7 @@ stage('Integration Test') {
timeout(time: max_time, unit: 'MINUTES') {
sh "${docker_run} ${ci_cpu} ./tests/scripts/task_ci_setup.sh"
sh "${docker_run} ${ci_cpu}
./tests/scripts/task_python_frontend_cpu.sh"
+ junit "./build/pytest-results/*.xml"
}
}
}
[tvm] branch ci-docker-staging updated (eb6dc25 -> 27bed74)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch ci-docker-staging in repository https://gitbox.apache.org/repos/asf/tvm.git. omit eb6dc25 Jenkinsfile changes for #7333. add 0d303b4 [Parser] Fix tokenizing inf (#7370) add f7e05c3 Improve op_type missing message (#7384) add 0bd259a [COMMUNITY] @hzfan -> reviewer (#7360) add 3635945 Refactor Dynamic to Static (#7368) add 0ab9c95 [Relay][Passes] Iterative A-normal Traversals (#7374) add de0ab4c Fix missing round(), floor(), ceil() for target C lowering (#7382) add da42924 [FFI] Improve error messages when array/map types do not match in function calls (#7330) add 618ef9e [TOPI] Add einsum operator (#6370) add 2e8133d [TFLite] Added check for dynamic range quantization (#7114) add 1de98be Generate requirements.txt from Python spec (#7289) add 30c110c [Bugfix][AutoScheduler] Fail to register ComputeDAG when deserializing tasks (#7395) add 9aec474 [CI] Temporary increase ci timeout (#7403) add f1b9663 [RPC] Replace timestamp with counter (#7389) add c118b08 Support negative pad values (#7375) add 38c9eb1 Fix Bug in Bilinear Interpolation and Add Deform Conv to PT FrontEnd (#7397) add d8313d0 [AutoScheduler] Support early_stopping per task (#7377) add 132cf6b [CI] Add back the tests after timeout adjusted (#7408) add 91e07e1 [Relay][Frontend][Onnx] Refactor where importer to support dynamic shapes. (#7394) add 4df530d Add cuda tags and unit test (#7410) add fc08430 check for dynamic rank before accessing value (#7414) add 1f846f0 [VM] Minor refactor for C++ memory alloc (#7413) add 9daf3fe Fix AutoScheduler for anaconda python (#7387) add 33f30af Fix compilation when Arm FP16 extensions are enabled (#7386) add 5103bb6 Jenkinsfile changes for #7333. (#7388) add 0e7e2dc [µTVM] Add VMWare to Reference VM instructions (#7221) add c789a29 Generate JUnitXML from pytest (#7407) add 79b6ef7 [FIX,CMAKE] Only compile runtime files once (#7417) new 27bed74 Enable JUnit parsing for Python tests This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (eb6dc25) \ N -- N -- N refs/heads/ci-docker-staging (27bed74) You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omit" are not gone; other references still refer to them. Any revisions marked "discard" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "add" were already present in the repository and have only been added to this reference. Summary of changes: CMakeLists.txt | 11 +- CONTRIBUTORS.md| 1 + Jenkinsfile| 12 +- apps/microtvm/reference-vm/base-box-tool.py| 68 +- apps/microtvm/reference-vm/zephyr/Vagrantfile | 10 + .../zephyr/base-box/Vagrantfile.packer-template| 7 + .../microtvm/reference-vm/zephyr/base-box/setup.sh | 24 +- include/tvm/ir/op.h| 2 +- include/tvm/node/container.h | 31 +- include/tvm/relay/expr_functor.h | 4 + include/tvm/runtime/packed_func.h | 73 +- include/tvm/topi/detail/tensor_utils.h | 95 ++- include/tvm/topi/einsum.h | 943 + include/tvm/topi/tags.h| 1 + python/.gitignore | 1 + python/gen_requirements.py | 615 ++ python/setup.py| 40 +- python/tvm/auto_scheduler/search_task.py | 13 +- python/tvm/auto_scheduler/task_scheduler.py| 47 +- python/tvm/auto_scheduler/workload_registry.py | 18 +- python/tvm/relay/frontend/onnx.py | 48 +- python/tvm/relay/frontend/pytorch.py | 27 + python/tvm/relay/frontend/tflite.py| 34 +- python/tvm/rpc/tracker.py | 10 +- python/tvm/topi/__init__.py| 1 + python/tvm/topi/einsum.py | 44 + .../tvm/topi/testing/deformable_conv2d_python.py | 26 +- python/tvm/topi/testing/roi_align_python.py| 34 +- python/tvm/topi/vision/rcnn/roi_
[tvm] branch main updated (5103bb6 -> 0e7e2dc)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 5103bb6 Jenkinsfile changes for #7333. (#7388) add 0e7e2dc [µTVM] Add VMWare to Reference VM instructions (#7221) No new revisions were added by this update. Summary of changes: apps/microtvm/reference-vm/base-box-tool.py| 68 ++ apps/microtvm/reference-vm/zephyr/Vagrantfile | 10 .../zephyr/base-box/Vagrantfile.packer-template| 7 +++ .../microtvm/reference-vm/zephyr/base-box/setup.sh | 24 ++-- tutorials/micro/micro_reference_vm.py | 12 ++-- 5 files changed, 98 insertions(+), 23 deletions(-)
[tvm] branch ci-docker-staging updated (7ae7214 -> eb6dc25)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch ci-docker-staging in repository https://gitbox.apache.org/repos/asf/tvm.git. discard 7ae7214 Jenkinsfile changes for #7333. add eb6dc25 Jenkinsfile changes for #7333. This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (7ae7214) \ N -- N -- N refs/heads/ci-docker-staging (eb6dc25) You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omit" are not gone; other references still refer to them. Any revisions marked "discard" are gone forever. No new revisions were added by this update. Summary of changes: Jenkinsfile | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-)
[tvm] branch main updated (3635945 -> 0ab9c95)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 3635945 Refactor Dynamic to Static (#7368) add 0ab9c95 [Relay][Passes] Iterative A-normal Traversals (#7374) No new revisions were added by this update. Summary of changes: include/tvm/relay/expr_functor.h | 4 ++ src/relay/analysis/util.cc| 12 ++ src/relay/ir/expr_functor.cc | 22 +++ src/relay/transforms/de_duplicate.cc | 20 -- src/relay/transforms/fold_constant.cc | 36 -- src/relay/transforms/fuse_ops.cc | 52 +- src/relay/transforms/type_infer.cc| 70 ++- 7 files changed, 175 insertions(+), 41 deletions(-)
[tvm] branch ci-docker-staging updated (f1a03cc -> 7ae7214)
This is an automated email from the ASF dual-hosted git repository.
moreau pushed a change to branch ci-docker-staging
in repository https://gitbox.apache.org/repos/asf/tvm.git.
discard f1a03cc Jenkinsfile changes for #7333.
add 7ae7214 Jenkinsfile changes for #7333.
This update added new revisions after undoing existing revisions.
That is to say, some revisions that were in the old version of the
branch are not in the new version. This situation occurs
when a user --force pushes a change and generates a repository
containing something like this:
* -- * -- B -- O -- O -- O (f1a03cc)
\
N -- N -- N refs/heads/ci-docker-staging (7ae7214)
You should already have received notification emails for all of the O
revisions, and so the following emails describe only the N revisions
from the common base, B.
Any revisions marked "omit" are not gone; other references still
refer to them. Any revisions marked "discard" are gone forever.
No new revisions were added by this update.
Summary of changes:
Jenkinsfile| 14 --
.../scripts/{task_ci_python_setup.sh => task_ci_setup.sh} | 0
2 files changed, 4 insertions(+), 10 deletions(-)
rename tests/scripts/{task_ci_python_setup.sh => task_ci_setup.sh} (100%)
[tvm] branch main updated (4f414fd -> 4142128)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from 4f414fd fix grad for zeros and ones (#7357) add 4142128 [BYOC][Verilator] change runtime registry function name (#7351) No new revisions were added by this update. Summary of changes: src/relay/backend/contrib/verilator/codegen.cc | 2 +- src/runtime/contrib/verilator/verilator_runtime.cc | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-)
[tvm] branch main updated (f7862e7 -> 4f414fd)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a change to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git. from f7862e7 [Relay][Frontend[Onnx] Add testing for output datatypes and fix related bugs. (#7364) add 4f414fd fix grad for zeros and ones (#7357) No new revisions were added by this update. Summary of changes: python/tvm/relay/op/_tensor_grad.py | 22 +++--- tests/python/relay/test_op_grad_level3.py | 49 ++- 2 files changed, 66 insertions(+), 5 deletions(-)
[tvm] branch main updated: add Verilator to CI (#7098)
This is an automated email from the ASF dual-hosted git repository. moreau pushed a commit to branch main in repository https://gitbox.apache.org/repos/asf/tvm.git The following commit(s) were added to refs/heads/main by this push: new 42eb55d add Verilator to CI (#7098) 42eb55d is described below commit 42eb55dda8f121fe572e99127372757826f8b892 Author: Luis Vega AuthorDate: Sat Jan 23 12:41:21 2021 -0800 add Verilator to CI (#7098) --- Jenkinsfile | 4 ++-- tests/scripts/task_config_build_cpu.sh | 1 + tests/scripts/task_config_build_i386.sh | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 67a41cd..0bf3a1b 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -46,9 +46,9 @@ // NOTE: these lines are scanned by docker/dev_common.sh. Please update the regex as needed. --> ci_lint = "tlcpack/ci-lint:v0.62" ci_gpu = "tlcpack/ci-gpu:v0.72" -ci_cpu = "tlcpack/ci-cpu:v0.71" +ci_cpu = "tlcpack/ci-cpu:v0.72-t0" ci_wasm = "tlcpack/ci-wasm:v0.70" -ci_i386 = "tlcpack/ci-i386:v0.71" +ci_i386 = "tlcpack/ci-i386:v0.72-t0" ci_qemu = "tlcpack/ci-qemu:v0.01" ci_arm = "tlcpack/ci-arm:v0.01" // <--- End of regex-scanned config. diff --git a/tests/scripts/task_config_build_cpu.sh b/tests/scripts/task_config_build_cpu.sh index 9a009b6..9ddf177 100755 --- a/tests/scripts/task_config_build_cpu.sh +++ b/tests/scripts/task_config_build_cpu.sh @@ -45,3 +45,4 @@ echo set\(USE_FLATBUFFERS_PATH \"/flatbuffers\"\) >> config.cmake echo set\(USE_ETHOSN /opt/arm/ethosn-driver\) >> config.cmake echo set\(USE_ETHOSN_HW OFF\) >> config.cmake echo set\(USE_VITIS_AI ON\) >> config.cmake +echo set\(USE_VERILATOR ON\) >> config.cmake diff --git a/tests/scripts/task_config_build_i386.sh b/tests/scripts/task_config_build_i386.sh index 8ed5f94..68e61c6 100755 --- a/tests/scripts/task_config_build_i386.sh +++ b/tests/scripts/task_config_build_i386.sh @@ -34,3 +34,4 @@ echo set\(CMAKE_CXX_COMPILER g++\) >> config.cmake echo set\(CMAKE_CXX_FLAGS -Werror\) >> config.cmake echo set\(USE_VTA_TSIM ON\) >> config.cmake echo set\(USE_VTA_FSIM ON\) >> config.cmake +echo set\(USE_VERILATOR ON\) >> config.cmake
