FrozenGene edited a comment on issue #4803: [WIP][Frontend] Asymmetric padding of convolution support URL: https://github.com/apache/incubator-tvm/pull/4803#issuecomment-581793013 Thanks for the quick response @anijain2305 ! > I can handle them in 2 separate PRs. For Conv2D attrs, I will have to put RFC to gather everybody thoughts on changing the Conv2D API. Not sure, if everybody will be happy with changing extensively used Conv2D API. Yes. I agree we should file a RFC, because this affects many aspects, even Conv1D, Conv3D, because we should unify these attrs too. > > @FrozenGene do you have any rough numbers for what is the padding overhead if we have it a separate operator? For C5 Cascade/Skylake servers, I don't see pad taking any significant time. So, just curious. (maybe bad schedule for other platforms) I am very sad that I lost the number. I don't know whether @Rasterer has record number. Previous testing on one arm device [i.MX6 ](https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i.mx-applications-processors/i.mx-6-processors:IMX6X_SERIES), ARM cortex A9 cpu, which has performance impact. Your skylake CPU is too strong so that we maybe can not observe significant overhead. Meanwhile, you could put an eye on this PR https://github.com/apache/incubator-tvm/pull/4807, it shouldn't fail on qnn mobilenet v1 test. Its logic is correct.
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