I have completed adopting the latest VSA update published at the start
of this thread to my GNU-buildable VSA version. I placed a tarball of
the sources at http://www.whiterocker.com/openvsa/openvsa_20080207.tar.gz
Please be aware this is all completely untested; there could be plenty
of typos
On Wed, Feb 06, 2008 at 06:30:23PM +0200, Mart Raudsepp wrote:
Signed-off-by: Mart Raudsepp [EMAIL PROTECTED]
Thanks, r3097 with some small cleanups.
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
--
Author: uwe
Date: 2008-02-08 10:59:58 +0100 (Fri, 08 Feb 2008)
New Revision: 3097
Modified:
trunk/util/flashrom/chipset_enable.c
Log:
This implements support for devices using AMD Geode companion chip
CS5536 that have the Boot ROM on NOR flash that is directly connected to
FLASH_CS3 (Boot
Author: uwe
Date: 2008-02-08 10:59:58 +0100 (Fri, 08 Feb 2008)
New Revision: 3097
Modified:
trunk/util/flashrom/chipset_enable.c
Log:
This implements support for devices using AMD Geode companion chip
CS5536 that have the Boot ROM on NOR flash that is directly connected to
FLASH_CS3 (Boot
Author: uwe
Date: 2008-02-08 11:10:57 +0100 (Fri, 08 Feb 2008)
New Revision: 3098
Modified:
trunk/util/flashrom/chipset_enable.c
Log:
Improve error handling and make RCONF_DEFAULT_MSR address be a constant.
Also, move a big code comment to the top of enable_flash_cs5536().
Signed-off-by: Mart
On 08.02.2008 12:51, Carl-Daniel Hailfinger wrote:
On 08.02.2008 06:54, ron minnich wrote:
This patch (which is NOT signed off) adds (or tries to) PIRQ support
for the alix1c.
it crashes and burns badly, however, I don' t know why.
You found the problem with LAR parsing of
Hello,
Here's a small further cleanup patch to the enable_flash_cs5536 function in
chipset_enable.c:
flashrom: further cleanups to enable_flash_cs5536
Remove the enable write to flash message, as the caller appears to already
report that.
Move the 'modprobe msr' suggestions to the first
On 08.02.2008 06:54, ron minnich wrote:
This patch (which is NOT signed off) adds (or tries to) PIRQ support
for the alix1c.
it crashes and burns badly, however, I don' t know why. Marc, is
0xf set up as memory in the v3 port? I am not sure.
I still have the suspicion that the VSA
Author: rminnich
Date: 2008-02-08 16:57:02 +0100 (Fri, 08 Feb 2008)
New Revision: 581
Modified:
coreboot-v3/device/pci_device.c
Log:
Trivial patch: for an id, use DEVICE_ID_PCI, not DEVICE_PATH_PCI.
Signed-off-by: Ronald G. Minnich [EMAIL PROTECTED]
Acked-by: Ronald G. Minnich [EMAIL
On 07.02.2008 20:29, Myles Watson wrote:
Coreboot-v3 calls the qemu board qemu-x86, but Coreboot-v2 calls it
qemu-i386. I think that qemu-x86 should be the preferred name.
Does anyone have any reservations about the switch to qemu-x86 in
Coreboot-v2?
Hm. Qemu also has an x86-64
On Feb 8, 2008 7:53 AM, ron minnich [EMAIL PROTECTED] wrote:
On Feb 8, 2008 3:51 AM, Carl-Daniel Hailfinger
[EMAIL PROTECTED] wrote:
On 08.02.2008 06:54, ron minnich wrote:
This patch (which is NOT signed off) adds (or tries to) PIRQ support
for the alix1c.
it crashes and burns
Hi All,
I have an HP Prolient DL145 server on order and want to use coreboot
with it. It uses the IWILL DK8_HTX motherboard and I want to order a
BIOS savior. Can someone please confirm that this IWILL motherboard uses
a SST 49LF004B Flash ?
Thanks,
Marco
--
coreboot mailing list
Hi, I'm getting a kind of errors, when I trying to compile refs.
Broadcom/blast with socket F cpu support, with the next error log
coreboot_ram.o(.text+0x724): In function `model_10xxx_init':
: undefined reference to `get_node_pci'
coreboot_ram.o(.text+0x743): In function `model_10xxx_init':
:
On 29.01.2008 19:58, Jouni Mettälä wrote:
On Jan 29, 2008 7:35 PM, Carl-Daniel Hailfinger wrote:
Yes flashrom doesn't recognize these chips (patched and unpatched)
AT-29C020, W29C020C-90B, supported by flashrom
Uniflash recognizes sst29ee010 chip and writes it. Chip is unsupported by
Quoting Corey Osgood [EMAIL PROTECTED]:
I apologize if this seems disorganized, I'm trying to work it out:
1: set up csr memory/io base in the nic. ami bios uses 0xff7ff000 for mem
base, and 0xdc01 as io base, these values should work to test with.
Datasheet contradicts itself, says bits 3:0
Hello,
I am working on adding board_enable code for Artec Group DBE61 and DBE62
boards to utils/flashrom to set up everything fully for flash writing to
work in all circumstances, but I've hit a problem in the infrastructure
code for mainboard selection handling that I'd like to discuss on how to
On 08.02.2008 20:08, Myles Watson wrote:
Sorry in advance that I only have time to report the problem. If no
one beats me to it I'll look into it a little more on Monday.
Something goes wrong when lzma is enabled (which it is by default)
I'm attaching my config which succeeds
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
I asked my contact for K8M890/K8T890CF datasheets (what needs to be done to get
them) already.
I will let know when there is something new. In the meanwhile someone can get
K8M890 lspci -xxx ? /me is quite curious.
Rudolf
-BEGIN PGP
On Feb 8, 2008 3:05 PM, Carl-Daniel Hailfinger
[EMAIL PROTECTED] wrote:
Within the tarball there is a file modification_notes.txt that
highlights what I have done. I'm hoping to foster some discussion on a
testing approach that lays somewhere between manual inspection and
slapping the
On 08.02.2008 18:53, Stefan Reinauer wrote:
Jordan Crouse wrote:
On 08/02/08 00:09 -0800, Chris Kilgour wrote:
I have completed adopting the latest VSA update published at the start
of this thread to my GNU-buildable VSA version. I placed a tarball of
the sources at
On 08.02.2008 17:13, Jordan Crouse wrote:
On 08/02/08 00:09 -0800, Chris Kilgour wrote:
I have completed adopting the latest VSA update published at the start
of this thread to my GNU-buildable VSA version. I placed a tarball of
the sources at
Patch to allow compiling on 64 bit hosts as well as that oldy but
goody, -fno-stack-protector.
Jordan
--
Jordan Crouse
Systems Software Development Engineer
Advanced Micro Devices, Inc.
[openvsa] Fix for 64 bit hosts, and add in our good friend -fno-stack-protector
Signed-off-by: Jordan Crouse
On 08.02.2008 02:02, ron minnich wrote:
This patch has LAR create segments for bss.
ron
Fix lar so that it parses .bss section headers.
This is not terribly clean but it works.
Signed-off-by: Ronald G. Minnich [EMAIL PROTECTED]
Tested with a qemu boot to work correctly.
Acked-by:
Author: hailfinger
Date: 2008-02-08 13:15:46 +0100 (Fri, 08 Feb 2008)
New Revision: 580
Modified:
coreboot-v3/util/lar/stream.c
Log:
Fix lar so that it parses .bss section headers.
This is not terribly clean but it works.
Signed-off-by: Ronald G. Minnich [EMAIL PROTECTED]
Tested with a
On 08/02/08 00:09 -0800, Chris Kilgour wrote:
I have completed adopting the latest VSA update published at the start
of this thread to my GNU-buildable VSA version. I placed a tarball of
the sources at http://www.whiterocker.com/openvsa/openvsa_20080207.tar.gz
Please be aware this is all
On 29.01.2008 18:59, Tiago Marques wrote:
Any ideas? From where should I start?
Try to erase a chip with flashrom -E (just erase, no write, no verify)
and then read back the contents with flashrom -r. Look at the
resulting file with xxd or hexdump and check if it is all 0xff.
I suspect that
Jordan Crouse wrote:
On 08/02/08 00:09 -0800, Chris Kilgour wrote:
I have completed adopting the latest VSA update published at the start
of this thread to my GNU-buildable VSA version. I placed a tarball of
the sources at http://www.whiterocker.com/openvsa/openvsa_20080207.tar.gz
Please
I'd say
Acked-by: Corey Osgood [EMAIL PROTECTED]
I don't really care what message gets put out there, hopefully board owners
either know or don't care what they've got, and developers should be able to
figure it out easy enough. These marketing names rarely make any sense
anyways, but just my 2
On 06.02.2008 21:54, Luc Verhaegen wrote:
On Wed, Feb 06, 2008 at 03:42:44PM -0500, Corey Osgood wrote:
Wonder if it's possible to set gmail's default reply to reply all. Anyways,
forgotten again, but I'll add some extra info to make it worthwhile. Here's
lspci -xxx from the vt8237r's lpc
Hi Jonathan,
sorry that your code is still unreviewed. I had a quick look over it, but
On 02.02.2008 20:41, [EMAIL PROTECTED] wrote:
Initial support for MSI MS-7135 (K8N Neo3) mainboard.
Signed-off-by: Jonathan A. Kollasch jakllsch at
so far it looks like I have some pretty great speakers, two talks from
AMD, one on the consumer market and another on chipsets; a talk from a
company on a board with an FPGA coprocessor (I'm working on another);
a good chance we'll get a talk from Sun.
I invite others to talk. I think we'd love
On 09.02.2008 01:31, ron minnich wrote:
so far it looks like I have some pretty great speakers, two talks from
AMD, one on the consumer market and another on chipsets; a talk from a
company on a board with an FPGA coprocessor (I'm working on another);
a good chance we'll get a talk from Sun.
The only fully open source implementation of EFI is based on coreboot.
Coreboot + tiano core provides a full open source EFI.
No EFI-based BIOS can make that statement.
Coreboot can reduce the costs of the platform, because
1. no per-unit license
2. distributed support model (same model as
Hi,
when promoting LinuxBIOS over the last few months I almost invariably
got the response: Why would anyone want to create a new BIOS? EFI is
the future.
EFI marketing seems to have successfully convinced many people by simple
repetition of their EFI is the future campaign. Back when we had the
Author: hailfinger
Date: 2008-02-09 03:03:06 +0100 (Sat, 09 Feb 2008)
New Revision: 3099
Modified:
trunk/util/flashrom/board_enable.c
Log:
Flashrom: Add board enable for VIA EPIA SP.
Signed-off-by: Luc Verhaegen [EMAIL PROTECTED]
Acked-by: Corey Osgood [EMAIL PROTECTED]
Acked-by: Peter Stuge
Author: hailfinger
Date: 2008-02-09 03:03:06 +0100 (Sat, 09 Feb 2008)
New Revision: 3099
Modified:
trunk/util/flashrom/board_enable.c
Log:
Flashrom: Add board enable for VIA EPIA SP.
Signed-off-by: Luc Verhaegen [EMAIL PROTECTED]
Acked-by: Corey Osgood [EMAIL PROTECTED]
Acked-by: Peter Stuge
On 09.02.2008 00:37, Corey Osgood wrote:
I'd say
Acked-by: Corey Osgood [EMAIL PROTECTED]
I don't really care what message gets put out there, hopefully board owners
either know or don't care what they've got, and developers should be able to
figure it out easy enough. These marketing names
Dear coreboot readers!
This is the automated build check service of coreboot.
The developer hailfinger checked in revision 3099 to
the coreboot source repository and caused the following
changes:
Change Log:
Flashrom: Add board enable for VIA EPIA SP.
Signed-off-by: Luc Verhaegen [EMAIL
#70: fix util/getpir so that the output will compile
--+-
Reporter: Jon Dufresne [EMAIL PROTECTED] | Owner: somebody
Type: defect |Status: new
changes to support PIRQ tables. This now builds,runs, loads FILO, and
loads linux.
But interrupts are still not set right. That's for tomorrow.
ron
This set of changes creates irq tables for alix1c and adds the functions
from v2 to install them. Linux boots fine but still doesn't find the
On Feb 9, 2008 2:36 AM, ron minnich [EMAIL PROTECTED] wrote:
Interrupts are up and working on the LX on v3! Ethernet, USB, etc. --
it's all working.
We may be close to moving all LX boards to v3. This is a big day.
patch attached.
ron
Awesome!
One thing I think you missed:
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