Luc Verhaegen wrote:
Anyone have any contact information for who reported this to begin
with?
Could look at wiki history to see who added it to the wiki at least.
Because that is the only thing that's standing in the way of adding
chipset/board support for this hw.
Mh - if you send a patch
Author: oxygene
Date: 2009-05-22 13:37:27 +0200 (Fri, 22 May 2009)
New Revision: 543
Modified:
trunk/board_enable.c
trunk/chipset_enable.c
trunk/flashrom.8
trunk/flashrom.c
trunk/satasii.c
Log:
A bunch of output beautifications and improvements, as well as doc
fixes:
- Update
On Fri, May 22, 2009 at 01:35:28PM +0200, Peter Stuge wrote:
Luc Verhaegen wrote:
Anyone have any contact information for who reported this to begin
with?
Could look at wiki history to see who added it to the wiki at least.
Ah, right; result: uwe added this late december, just a month
Author: uwe
Date: 2009-05-22 15:18:38 +0200 (Fri, 22 May 2009)
New Revision: 544
Modified:
trunk/README
Log:
Add website section (trivial).
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
Acked-by: Uwe Hermann u...@hermann-uwe.de
Modified: trunk/README
Hello all,
First thanks to Uwe for nic3com support and to Mats Erik (IIRC) for helping
with (or atleast pointing out the lack of) 3C905B support - i just tested a
SST 29EE010 on an 3C905B-TXNM that had been useless for a while - works :)
Anyways, does anyone know how big flash chips these 3com's
Urja Rannikko wrote:
Anyways, does anyone know how big flash chips these 3com's support?
The SST i tested is 128k - i can propably (given time) test 256k
also, but just curious.
The theoretical limit is 512k, which would use all of the 32 PLCC
leads.
But it really depends on how many address
2009/5/22 Urja Rannikko urja...@gmail.com
Hello all,
First thanks to Uwe for nic3com support and to Mats Erik (IIRC) for helping
with (or atleast pointing out the lack of) 3C905B support - i just tested a
SST 29EE010 on an 3C905B-TXNM that had been useless for a while - works :)
Anyways,
Idwer Vollering wrote:
http://www.shikadi.net/hwwiki/Flash_chips
This links to http://ctflasher.sourceforge.net/ which has drivers for
programming flash chips on Intel, Realtek and VIA NICs as well.
//Peter
--
coreboot mailing list: coreboot@coreboot.org
Urja Rannikko wrote:
Hello all,
First thanks to Uwe for nic3com support and to Mats Erik (IIRC) for
helping with (or atleast pointing out the lack of) 3C905B support - i
just tested a SST 29EE010 on an 3C905B-TXNM that had been useless for a
while - works :)
Anyways, does anyone know how
Ward Vandewege wrote:
Hmm. So, cdrom firmware bug?
Does FILO behave the same way?
Can you try with a few different optical drives?
//Peter
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
On Fri, May 22, 2009 at 03:45:02PM +0200, Peter Stuge wrote:
Urja Rannikko wrote:
Anyways, does anyone know how big flash chips these 3com's support?
The SST i tested is 128k - i can propably (given time) test 256k
also, but just curious.
The theoretical limit is 512k, which would use
On Fri, May 22, 2009 at 03:51:45PM +0200, Peter Stuge wrote:
Idwer Vollering wrote:
http://www.shikadi.net/hwwiki/Flash_chips
This links to http://ctflasher.sourceforge.net/ which has drivers for
programming flash chips on Intel, Realtek and VIA NICs as well.
Indeed, and I have patches
Author: ward
Date: 2009-05-22 18:03:04 +0200 (Fri, 22 May 2009)
New Revision: 4295
Modified:
trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb
Log:
Fix MAINBOARD_PART_NUMBER to be h8dme, I forgot to change it from the h8dmr
tree it was copied from.
This is a trivial patch.
log:
Add support for probe and read of Intel 28F001BX-T and BX-B.
Signed-off-by: Urja Rannikko urja...@gmail.com
--- more detail: --
Erase write support wont be this easy - the chips need 12V Vpp
(needs a hardware hack or a supporting mb) and they have a very weird
layout and are old.
Test
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer ward checked in revision 4295 to
the coreboot repository. This caused the following
changes:
Change Log:
Fix MAINBOARD_PART_NUMBER to be h8dme, I forgot to change it from the h8dmr
tree it was copied from.
On Thu, May 21, 2009 at 09:19:04PM -0400, Kevin O'Connor wrote:
On Thu, May 21, 2009 at 01:03:30PM -0400, Ward Vandewege wrote:
On Thu, May 21, 2009 at 12:13:04PM -0400, Ward Vandewege wrote:
That worked!
Great!
OK, I can now get to the boot menu, which is great.
Ideally though,
Author: uwe
Date: 2009-05-22 20:17:06 +0200 (Fri, 22 May 2009)
New Revision: 4296
Modified:
trunk/util/getpir/code_gen.c
Log:
Make the getpir output look less crappy and add a license
header template, as people keep forgetting them.
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
Acked-by: Uwe
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer uwe checked in revision 4296 to
the coreboot repository. This caused the following
changes:
Change Log:
Make the getpir output look less crappy and add a license
header template, as people keep forgetting
Hello,
I am interested to participate in development of coreboot support for VIA
VX8xx+Nano. I have experience in adaptation of LinuxBIOS for GeodeLX platforms
in a past. And I have experience in low-level programming and vendor BIOSes
(GS, Phoenix) adaptation for other VIA chipsets (CN400,
Hello,
I am interested to participate in development of coreboot support for VIA
VX8xx+Nano. I have experience in adaptation of LinuxBIOS for GeodeLX platforms
in a past. And I have experience in low-level programming and vendor BIOSes
(GS, Phoenix) adaptation for other VIA chipsets (CN400,
There is no work for Nano yet but I believe the C7 is nearly identical.
The VX800 work will be public in the next few days.
-Bari
Konsstantin Lazarev wrote:
Hello,
I am interested to participate in development of coreboot support for
VIA VX8xx+Nano. I have experience in adaptation of
Author: uwe
Date: 2009-05-23 02:56:49 +0200 (Sat, 23 May 2009)
New Revision: 545
Modified:
trunk/board_enable.c
Log:
Autodetection support and write-enable for the MSI KT4 Ultra.
Thanks Christian Ruppert spook...@gmail.com for testing on hardware.
(also: Fix a typo and some whitespace while
On Sat, May 23, 2009 at 02:56:50AM +0200, s...@coreboot.org wrote:
+ {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0,
msi,kt4ultra,MSI, KT4 Ultra,
board_msi_kt4v},
For future reference, here's the lspci from that board.
00:00.0 Host bridge:
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