[coreboot] amd-mct_ddr3-ChannelB Patch

Hi, Multi-DIMMS on AMD ddr3 MCT channel B works. Signed-off-by: Kerry She kerry@amd.com amd-mct_ddr3-channelB.patch Description: amd-mct_ddr3-channelB.patch -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] amd mct_ddr3 trivial patch

Hi, Trivial syntax correction of AMD mct_ddr3 dir. Signed-off-by: Kerry She kerry@amd.com Acked-by: Kerry She kerry@amd.com amd-mct_ddr3-trivial-syntax.patch Description: amd-mct_ddr3-trivial-syntax.patch -- coreboot mailing list: coreboot@coreboot.org

[coreboot] [commit] r5747 - trunk/src/northbridge/amd/amdmct/mct_ddr3

Author: zbao Date: Mon Aug 30 09:24:13 2010 New Revision: 5747 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5747 Log: Trivial syntax correction of AMD mct_ddr3 dir. Signed-off-by: Kerry She kerry@amd.com Acked-by: Kerry She kerry@amd.com Modified:

[coreboot] [commit] r5748 - in trunk/src/northbridge/amd/amdmct: mct_ddr3 wrappers

Author: zbao Date: Mon Aug 30 09:31:31 2010 New Revision: 5748 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5748 Log: Multi-DIMMS on AMD ddr3 MCT channel B works. Signed-off-by: Kerry She kerry@amd.com Acked-by: Stefan Reinauer ste...@coresystems.de Modified:

[coreboot] AMD ddr MCT channelB patch

Hi, Multi-DIMMS on AMD ddr MCT channel B fixed. Signed-off-by: Kerry She kerry@amd.com amd-mct-channelB.patch Description: amd-mct-channelB.patch -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH] added ich10r gpio support to intel tool

I have attached a patch for ich10r support for dumping gpio registers. I am looking for comments and a possible committer. Thanks, wt inteltool_add_ich10r_gpio.diff Description: Binary data -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] AMD ddr MCT channelB patch

Hi, Multi-DIMMS on AMD ddr MCT channel B fixed. Signed-off-by: Kerry She kerry@amd.com mailto:kerry@amd.com Acked-by: Stefan Reinauer ste...@coresystems.de -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [commit] r5749 - trunk/src/northbridge/amd/amdmct/mct

Author: kerry Date: Mon Aug 30 11:40:41 2010 New Revision: 5749 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5749 Log: Multi-DIMMS on AMD ddr2 MCT channel B fixed. Signed-off-by: Kerry She kerry@amd.com Acked-by: Stefan Reinauer ste...@coresystems.de Modified:

Re: [coreboot] [PATCH] added ich10r gpio support to intel tool

Am Montag, den 30.08.2010, 01:39 -0700 schrieb Warren Turkal: I have attached a patch for ich10r support for dumping gpio registers. Thank you for your patch. I am looking for comments and a possible committer. Please take a look at the Development Guideline and especially the sign-off

[coreboot] [PATCH 1/3] mPGA479M Sockets can take Intel Mobile Celeron. The 1.2GHz model has CPUID F29 This adds them to the list of CPUs for that socket.

Signed-off-by: Andreas Schultz aschu...@tpip.net --- src/cpu/intel/socket_mPGA479M/Kconfig |1 + src/cpu/intel/socket_mPGA479M/Makefile.inc |2 ++ 2 files changed, 3 insertions(+), 0 deletions(-) diff --git a/src/cpu/intel/socket_mPGA479M/Kconfig

[coreboot] [PATCH 0/3] i855 support

Hi, Here is a series of patches wich improve i855 support and a new board with that chipset. The board boots successfully with Seabios into Linux! There are still a few blacks left to filled in (undocumented chipset registers, some RAM parameters i have no idea how to compute). So any comment

[coreboot] [PATCH 3/3] support for Lanner EM-8510 Board

Signed-off-by: Andreas Schultz aschu...@tpip.net --- src/mainboard/Kconfig |8 ++ src/mainboard/lanner/Kconfig |8 ++ src/mainboard/lanner/em8510/Kconfig | 38 +++ src/mainboard/lanner/em8510/Makefile.inc | 21 ++

[coreboot] [PATCH 2/3] rework i855GM/i855GME support

Signed-off-by: Andreas Schultz aschu...@tpip.net --- src/northbridge/intel/i855/Kconfig | 30 + src/northbridge/intel/i855/i855.h| 76 +++ src/northbridge/intel/i855/northbridge.c | 21 + src/northbridge/intel/i855/raminit.c | 1036 +-

[coreboot] util directory

Inside util/abuild we have two files: abuild and abuild.1 What language do they have written with? What is their functions in short? Are they necessary for building a coreboot image? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] util directory

Inside util/abuild we have two files: abuild and abuild.1 What language do they have written with? abuild is a shell script. abuild.1 is a man page What is their functions in short? Find out yourself by typing man ./abuild.1 in the abuild directory. Are they necessary for building a

[coreboot] Trac reminder: list of new ticket(s)

Ticket Owner Status Description #167 ste...@coresystems.de new Support for new ION2 (Intel NM10 chipset) #164 ste...@coresystems.de new Building Coreboot v4 r/5554 fails mysteriously on Debian lenny and etch (x86)

Re: [coreboot] Building coreboot BIOS on a Windows computer

On Wed, Aug 25, 2010 at 10:44 PM, Scott sc...@notabs.org wrote: Hello coreboot folks, I know the developers here use linux, but many other bios developers are more comfortable with windows. Fortunately, it is easy to build coreboot using a Windows machine. The example below demonstrates using

[coreboot] [PATCH] restructure mainboard Kconfigs

Hi, In my last mail I described some restructuring to make (user visible) options in the board specific Kconfig files possible (i.e. don't source from within choice/endchoice). Another change I'd like to add is to move MAINBOARD_VENDOR and MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID to the vendor's

[coreboot] [commit] r5750 - trunk/src/cpu/intel/socket_mPGA479M

Author: stepan Date: Mon Aug 30 18:16:01 2010 New Revision: 5750 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5750 Log: mPGA479M Sockets can take Intel Mobile Celeron. The 1.2GHz model has CPUID F29. This adds them to the list of CPUs for that socket. Signed-off-by: Andreas Schultz

[coreboot] [commit] r5751 - trunk/src/northbridge/intel/i855

Author: stepan Date: Mon Aug 30 18:19:04 2010 New Revision: 5751 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5751 Log: Rework i855GM/i855GME support Signed-off-by: Andreas Schultz aschu...@tpip.net Acked-by: Stefan Reinauer ste...@coresystems.de ---

[coreboot] [commit] r5752 - in trunk/src/mainboard: . lanner lanner/em8510

Author: stepan Date: Mon Aug 30 18:22:22 2010 New Revision: 5752 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5752 Log: Support for Lanner EM-8510 Board Signed-off-by: Andreas Schultz aschu...@tpip.net Acked-by: Stefan Reinauer ste...@coresystems.de --- src/mainboard/Kconfig

[coreboot] build service results for r5750

Dear coreboot readers! This is the automatic build system of coreboot. The developer stepan checked in revision 5750 to the coreboot repository. This caused the following changes: Change Log: mPGA479M Sockets can take Intel Mobile Celeron. The 1.2GHz model has CPUID F29. This adds them to the

Re: [coreboot] Building coreboot BIOS on a Windows computer

-Original Message- From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On Behalf Of Marc Jones Sent: Monday, August 30, 2010 10:02 AM To: Scott Cc: coreboot@coreboot.org Subject: Re: [coreboot] Building coreboot BIOS on a Windows computer On Wed, Aug 25, 2010 at

[coreboot] [commit] r5753 - trunk/src/northbridge/intel/i855

Author: stepan Date: Mon Aug 30 18:32:23 2010 New Revision: 5753 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5753 Log: This file was missing from r5751. Signed-off-by: Andreas Schultz aschu...@tpip.net Acked-by: Stefan Reinauer ste...@coresystems.de Added:

[coreboot] [commit] r5755 - trunk/src/mainboard/intel/mtarvon

Author: stepan Date: Mon Aug 30 18:52:48 2010 New Revision: 5755 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5755 Log: Fix intel mtarvon compilation by switching it over to CAR. This should be unproblematic, as there are other boards with the same socket that work with CAR already.

Re: [coreboot] [PATCH 3/3] support for Lanner EM-8510 Board

On 8/30/10 12:10 PM, Andreas Schultz wrote: Signed-off-by: Andreas Schultz aschu...@tpip.net Dear Andreas, glad to see you had some success with coreboot! thank you very much for your contributions! I checked in your patches in r5750-r5753 Best regards, Stefan -- coreboot mailing list:

Re: [coreboot] [PATCH] restructure mainboard Kconfigs

On 8/30/10 5:47 PM, Jens Rottmann wrote: Hi, In my last mail I described some restructuring to make (user visible) options in the board specific Kconfig files possible (i.e. don't source from within choice/endchoice). Another change I'd like to add is to move MAINBOARD_VENDOR and

[coreboot] [PATCH] CACHE_AS_RAM

See patch We call this cache as ram everywhere, so let's call it the same in Kconfig Signed-off-by: Stefan Reinauer ste...@coresystems.de Index: include/assert.h === --- include/assert.h(revision 5749) +++ include/assert.h

[coreboot] build service results for r5751

Dear coreboot readers! This is the automatic build system of coreboot. The developer stepan checked in revision 5751 to the coreboot repository. This caused the following changes: Change Log: Rework i855GM/i855GME support Signed-off-by: Andreas Schultz aschu...@tpip.net Acked-by: Stefan

Re: [coreboot] [PATCH] CACHE_AS_RAM

Acked-by: Myles Watson myle...@gmail.com Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] CACHE_AS_RAM

Stefan Reinauer wrote: We call this cache as ram everywhere, so let's call it the same in Kconfig Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Peter Stuge pe...@stuge.se -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] build service results for r5752

Dear coreboot readers! This is the automatic build system of coreboot. The developer stepan checked in revision 5752 to the coreboot repository. This caused the following changes: Change Log: Support for Lanner EM-8510 Board Signed-off-by: Andreas Schultz aschu...@tpip.net Acked-by: Stefan

[coreboot] build service results for r5753

Dear coreboot readers! This is the automatic build system of coreboot. The developer stepan checked in revision 5753 to the coreboot repository. This caused the following changes: Change Log: This file was missing from r5751. Signed-off-by: Andreas Schultz aschu...@tpip.net Acked-by: Stefan

[coreboot] [commit] r5756 - in trunk/src: console cpu cpu/amd/model_10xxx cpu/amd/model_fxx cpu/amd/model_gx2 cpu/amd/model_lx cpu/intel/socket_FC_PGA370 cpu/x86/mtrr include include/cpu/x86 lib mainb

Author: stepan Date: Mon Aug 30 19:53:13 2010 New Revision: 5756 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5756 Log: We call this cache as ram everywhere, so let's call it the same in Kconfig Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Myles Watson

[coreboot] build service results for r5754

Dear coreboot readers! This is the automatic build system of coreboot. The developer stepan checked in revision 5754 to the coreboot repository. This caused the following changes: Change Log: Restructured all vendors' Kconfig files to no longer source the boards' Kconfigs from within the

[coreboot] build service results for r5755

Dear coreboot readers! This is the automatic build system of coreboot. The developer stepan checked in revision 5755 to the coreboot repository. This caused the following changes: Change Log: Fix intel mtarvon compilation by switching it over to CAR. This should be unproblematic, as there are

Re: [coreboot]  [PATCH] Generate multiboot tabl es after and from coreboot tables

Am 30.08.2010 20:54, schrieb Juhana Helovuo: Hello, The attached patch adds all the memory memory ranges in the coreboot tables also to the multiboot tables. It is useful e.g. when booting Linux with Grub2 payload, since then Linux gets the Coreboot memory map via multiboot tables. This

Re: [coreboot] Alix.2D3 / Coreboot v4 support

On Mon, Aug 30, 2010 at 9:39 PM, Patrick Georgi patr...@georgi-clan.dewrote: Am 30.08.2010 20:37, schrieb Aurélien: a) apply the patch as it is, and also remove RAMBASE 0x4000 to all the Geode LX based boards, at the risk of maybe breaking coreboot on them. I think the problem is that it

Re: [coreboot] Alix.2D3 / Coreboot v4 support

On Wed, Aug 25, 2010 at 5:27 PM, Patrick Georgi patr...@georgi-clan.dewrote: Loading stage image. Stage: loading fallback/coreboot_ram @ 0x10 (114688 bytes), entry @ 0x10 lzma: Decoding error = 1 CBFS: LZMA decompression failed! Loading stage failed! --- hangs here --- This

[coreboot] [PATCH] Use mainboard Kconfig option for AMD rumba

Thanks to Jens for his patch that makes this work! Signed-off-by: Myles Watson myle...@gmail.com Thanks, Myles Index: svn/src/mainboard/amd/rumba/Kconfig === --- svn.orig/src/mainboard/amd/rumba/Kconfig +++

[coreboot] [commit] r5757 - trunk/src/devices/oprom/yabel

Author: myles Date: Mon Aug 30 23:52:38 2010 New Revision: 5757 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5757 Log: Make yabel work for non-zero bus numbers. The link_num is not the bus number. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Myles Watson

[coreboot] build service results for r5757

Dear coreboot readers! This is the automatic build system of coreboot. The developer myles checked in revision 5757 to the coreboot repository. This caused the following changes: Change Log: Make yabel work for non-zero bus numbers. The link_num is not the bus number. Signed-off-by: Myles

Re: [coreboot] [PATCH 0/3] i855 support

2010/8/30 Andreas Schultz aschu...@tpip.net Hi, Here is a series of patches wich improve i855 support and a new board with that chipset. The board boots successfully with Seabios into Linux! Nice work. Can you show the output from the console (serial output) ? Off topic: I'm asking this

Re: [coreboot] [PATCH] added ich10r gpio support to intel tool

I clearly included the patch without my sign off. Here's another exported from my git tree. BTW, is there a git tree that is maintained and up to date? I'd rather not use git svn if I could avoid it. Thanks, wt On Mon, Aug 30, 2010 at 3:16 AM, Paul Menzel paulepan...@users.sourceforge.net

Re: [coreboot] [PATCH] added ich10r gpio support to intel tool

On Mon, 2010-08-30 at 18:52 -0700, Warren Turkal wrote: BTW, is there a git tree that is maintained and up to date? I'd rather not use git svn if I could avoid it. Thanks, wt Hi Warren, I have a hourly cron job keeping this git tree updated: git://github.com/ngwill/coreboot.git Regards,

[coreboot] (no subject)

Get Byte65/66 for register manufacture ID code. RegMan1Present will be used in write levelization training. Signed-off-by: Zheng Bao zheng@amd.com Index: src/northbridge/amd/amdmct/mct_ddr3/mct_d.c === ---

[coreboot] [patch]: AMD DDR3 Register manufacure feature

Get Byte65/66 for register manufacture ID code. RegMan1Present will be used in write levelization training. Signed-off-by: Zheng Bao zheng@amd.com Index: src/northbridge/amd/amdmct/mct_ddr3/mct_d.c === ---