[coreboot] [PATCH]mirror fix about superio makefile

see the patch Signed-off-by: Wang Qing Pei wangqing...@gmail.com Best wishes Wang Qing Pei Phone: 86+18930528086 Index: util/superiotool/Makefile === --- util/superiotool/Makefile (revision 6049) +++ util/superiotool/Makefile

[coreboot] [PATCH]adjust some code/comment of sb700 sata init

the inline comment of sata_init function seems not placed correctly. rearrange it. Signed-off-by: Wang Qing Pei wangqing...@gmail.com Best wishes Wang Qing Pei Phone: 86+18930528086 Index: src/southbridge/amd/sb700/sb700_sata.c ===

[coreboot] [PATCH]disable dev3 under ma78gm-us2h

disable bus 0 dev 3 pci bridge for ma78gm-us2h does not have this slot. Signed-off-by: Wang Qing Pei wangqing...@gmail.com Best wishes Wang Qing Pei Phone: 86+18930528086 Index: src/mainboard/gigabyte/ma78gm/devicetree.cb === ---

[coreboot] [PATCH] Restructure i3100 Super I/O driver to match the rest of the codebase

See patch. Build-tested against the i3100 boards (e.g. Truxton). Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org Restructure i3100 Super I/O driver to match the rest of the codebase. - i3100_early_serial.c: - Split

Re: [coreboot] [PATCH]disable dev3 under ma78gm-us2h

On Tue, Nov 9, 2010 at 2:09 AM, Qing Pei Wang wangqing...@gmail.com wrote: disable bus 0 dev 3 pci bridge for ma78gm-us2h does not have this slot. Signed-off-by: Wang Qing Pei wangqing...@gmail.com Acked-by: Marc Jones marcj...@gmail.com -- http://se-eng.com -- coreboot mailing list:

[coreboot] [commit] r6050 - trunk/src/mainboard/asus/m2v

Author: ruik Date: Tue Nov 9 23:11:00 2010 New Revision: 6050 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6050 Log: Add pirq table for ASUS M2V. Signed-off-by: Tobias Diedrich ranma+coreb...@tdiedrich.de Acked-by: Rudolf Marek r.ma...@assembler.cz Added:

Re: [coreboot] [patch 10/16] Add M2V pirq table

Acked-by: Rudolf Marek r.ma...@assembler.cz And commited too. Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [commit] r6051 - trunk/src/mainboard/asus/m2v

Author: ruik Date: Tue Nov 9 23:18:28 2010 New Revision: 6051 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6051 Log: Add acpi tables and dsdt. Signed-off-by: Tobias Diedrich ranma+coreb...@tdiedrich.de Acked-by: Rudolf Marek r.ma...@assembler.cz Added:

Re: [coreboot] [patch 13/16] Add PIRQ_ROUTE support for vt8237.

On 7.11.2010 13:46, Tobias Diedrich wrote: + pdev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); Can I haz S and R too please? Thanks, Rudolf -- coreboot mailing list: coreboot@coreboot.org

[coreboot] [commit] r6052 - trunk/src/cpu/amd/mtrr

Author: ruik Date: Tue Nov 9 23:31:11 2010 New Revision: 6052 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6052 Log: This fixes a FIXME in src/cpu/amd/mtrr/amd_mtrr.c and shuts up the Linux kernel, which was previously complaining that the MTRR setup is wrong, if the cpu supports

Re: [coreboot] [patch 15/16] Query cpu instead of usingCONFIG_CPU_ADDR_BITS on AMD cpus

Committed revision 6052. With a MSR to cpuid comment fix. Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [patch 11/16] Add M2V mptable

Updated for recent mptable_init(). Add mptable for ASUS M2V. Signed-off-by: Tobias Diedrich ranma+coreb...@tdiedrich.de --- Index: src/mainboard/asus/m2v/mptable.c === --- /dev/null 1970-01-01 00:00:00.0 + +++

Re: [coreboot] [patch 12/16] Add M2V basic ACPI support.

Add acpi tables and dsdt. Signed-off-by: Tobias Diedrich ranma+coreb...@tdiedrich.de Acked-by: Rudolf Marek r.ma...@assembler.cz And commited too. Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Debugging facility improvements

Uwe Hermann wrote: Debugging facility improvements. - Hook up malloc() debug code via CONFIG_DEBUG_MALLOC. Only show it in menuconfig if at least DEBUG or SPEW are selected as loglevel, as this code does additional printk(BIOS_DEBUG, ...) calls which would otherwise not be visible

Re: [coreboot] [PATCH]mirror fix about superio makefile

2010/11/9 Qing Pei Wang wangqing...@gmail.com see the patch Nack. Please don't change this, or this will happen (demonstrated using FreeBSD 8.1 + libpci 3.1.7 + gmake-3.81): $ gmake clean gmake rm -f superiotool *.o gcc -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing

[coreboot] [commit] r6053 - trunk/src/superio/ite/it8661f

Author: uwe Date: Wed Nov 10 01:08:42 2010 New Revision: 6053 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6053 Log: ITE IT8661F changes to match the common code structure. - it8661f_enable_serial() is now in the usual format, using pnp_* functions. - Factor out

[coreboot] [commit] r6054 - in trunk/src: . lib

Author: uwe Date: Wed Nov 10 01:14:32 2010 New Revision: 6054 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6054 Log: Debugging facility improvements. - Hook up malloc() debug code via CONFIG_DEBUG_MALLOC. Only show it in menuconfig if at least DEBUG or SPEW are selected as

Re: [coreboot] [PATCH] Debugging facility improvements

On Wed, Nov 10, 2010 at 12:35:40AM +0100, Peter Stuge wrote: Acked-by: Peter Stuge pe...@stuge.se Thanks, r6054. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org -- coreboot mailing list: coreboot@coreboot.org

[coreboot] build service results for r6054

Dear coreboot readers! This is the automatic build system of coreboot. The developer uwe checked in revision 6054 to the coreboot repository. This caused the following changes: Change Log: Debugging facility improvements. - Hook up malloc() debug code via CONFIG_DEBUG_MALLOC. Only show it in

Re: [coreboot] [patch 13/16] Add PIRQ_ROUTE support for vt8237.

Rudolf Marek wrote: On 7.11.2010 13:46, Tobias Diedrich wrote: +pdev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); Can I haz S and R too please? Sure: Add PIRQ_ROUTE support for vt8237. The only southbridge having a

[coreboot] [PATCH] Dynamically generate PNP0C02 mainboard resources in SSDT

Dynamically generate PNP0C02 mainboard resources in SSDT While adding the area between TOM1 and 4GB to \SB.PCI0._CRS seems to be the easiest way to get both Linux and Windows happy, it is not quite correct because reserved areas like APIC, MMCONF etc. ranges need to be excluded. This is a proof

[coreboot] [commit] r6055 - in trunk/src: . lib

Author: stuge Date: Wed Nov 10 03:00:32 2010 New Revision: 6055 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6055 Log: Ensure that config options hidden by r6054 have defaults, and fix MALLOCDBG() Signed-off-by: Peter Stuge pe...@stuge.se Acked-by: Peter Stuge pe...@stuge.se

[coreboot] [commit] r6056 - trunk/src/northbridge/amd/amdk8

Author: stuge Date: Wed Nov 10 03:12:05 2010 New Revision: 6056 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6056 Log: Make amdk8 printk_raminit() accept just a single string parameter The function is called with no format specifiers in the first parameter throughout the code, so it

[coreboot] build service results for r6055

Dear coreboot readers! This is the automatic build system of coreboot. The developer stuge checked in revision 6055 to the coreboot repository. This caused the following changes: Change Log: Ensure that config options hidden by r6054 have defaults, and fix MALLOCDBG() Signed-off-by: Peter

Re: [coreboot] [commit] r6055 - in trunk/src: . lib

Modified: trunk/src/lib/malloc.c == --- trunk/src/lib/malloc.cWed Nov 10 01:14:32 2010(r6054) +++ trunk/src/lib/malloc.cWed Nov 10 03:00:32 2010(r6055) @@ -4,7 +4,7 @@ #if

Re: [coreboot] [commit] r6055 - in trunk/src: . lib

Myles Watson wrote: This would be the easy place to make sure that you could see the messages. #define MALLOCDBG(x...) printk(CONFIG_DEFAULT_CONSOLE_LOGLEVEL, x) Very nice. It would allow to select individual debugging regardless of loglevel otherwise. I quite like that! //Peter -- coreboot

Re: [coreboot] [commit] r6055 - in trunk/src: . lib

On 09.11.2010, at 18:08, Myles Watson myle...@gmail.com wrote: Modified: trunk/src/lib/malloc.c == --- trunk/src/lib/malloc.cWed Nov 10 01:14:32 2010(r6054) +++ trunk/src/lib/malloc.cWed Nov 10 03:00:32

Re: [coreboot] build service results for r6054

This is a regression. It's the maximum loglevel not the default log level that counts. Please fix or revert. Stefan On 09.11.2010, at 16:52, repository service s...@coreboot.org wrote: Dear coreboot readers! This is the automatic build system of coreboot. The developer uwe checked in

Re: [coreboot] [commit] r6055 - in trunk/src: . lib

Stefan Reinauer wrote: This would be the easy place to make sure that you could see the messages. #define MALLOCDBG(x...) printk(CONFIG_DEFAULT_CONSOLE_LOGLEVEL, x) I think keeping them at SPEW is fine,... Otherwise we end up with images printing that information at ie error log level

Re: [coreboot] [commit] r6055 - in trunk/src: . lib

On Tue, Nov 9, 2010 at 7:53 PM, Stefan Reinauer stefan.reina...@coresystems.de wrote: On 09.11.2010, at 18:08, Myles Watson myle...@gmail.com wrote: Modified: trunk/src/lib/malloc.c == --- trunk/src/lib/malloc.c  

[coreboot] [PATCH] Avoid hang when 4GB or more DRAM is installed on AMD RS780 UMA systems

Avoid hang when 4GB or more DRAM is installed on AMD RS780 UMA systems. -- When building for UMA, reduce the limit for DRAM below 4GB from E000 to C000. This is needed to accomodate the UMA frame buffer. -- Correct problem where msr C0010010 bits 21 and 22 (MtrrTom2En and