We have the following definition for CC:
CC:=gcc -Wa,--divide -fno-stack-protector -Wl,--build-id=none
I wonder if any one can explain the options, --divide and --build-id.
Thank you.
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Stefan Reinauer wrote:
On 11/26/10 2:28 PM, Uwe Hermann wrote:
See patch.
Uwe.
Since it's amd specific (in a sense that it's not much benefit and only
used on amd based boards), we should move it to cpu/amd/acpi or
cpu/amd/amdk8/acpi?
It doesn't look amd-specific though.
At the very
ali hagigat wrote:
We have the following definition for CC:
CC:=gcc -Wa,--divide -fno-stack-protector -Wl,--build-id=none
I wonder if any one can explain the options, --divide and --build-id.
Thank you.
-Wl,foo is a linker option, please look at the ld manpage.
Similarily, -Wa,foo is an
Author: ranma
Date: Sat Nov 27 10:40:16 2010
New Revision: 6127
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6127
Log:
After finding the missing bit poweroff works now.
I cleaned up the patch and moved most of the dsdt.dsl and
acpi_tables.c into the southbrige/northbridge directory.
Stefan Reinauer wrote:
On 11/26/10 6:43 PM, Tobias Diedrich wrote:
After finding the missing bit poweroff works now.
I cleaned up the patch and moved most of the dsdt.dsl and
acpi_tables.c into the southbrige/northbridge directory.
Updated patch should fix abuild error and incorporates
Thank you for the reply but:
Documentation does not explain --divide!!
On Sat, Nov 27, 2010 at 12:58 PM, Tobias Diedrich
ranma+coreb...@tdiedrich.de wrote:
ali hagigat wrote:
We have the following definition for CC:
CC:=gcc -Wa,--divide -fno-stack-protector -Wl,--build-id=none
I wonder if
Am 27.11.2010 11:02, schrieb ali hagigat:
Thank you for the reply but:
Documentation does not explain --divide!!
It's getting tiresome:
http://www.coreboot.org/pipermail/coreboot/2010-September/060130.html
http://www.coreboot.org/pipermail/coreboot/2010-September/060138.html
That was you who
Hello,
I am in desperate need of a full (all tables) ACPI dump from somone with a
i852 or i855 chipset. You can send it to me offlist if you like. Thanks in
advance.
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
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coreboot mailing list: coreboot@coreboot.org
Author: ranma
Date: Sat Nov 27 15:44:19 2010
New Revision: 6128
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6128
Log:
- Add support for Intel Pentium III MSRs
- pmbase is on southbridge function 3 on I82371XX
Signed-off-by: Tobias Diedrich ranma+coreb...@tdiedrich.de
Acked-by:
#169: ASUS P4PE-X/SE.
+--
Reporter: anonymous| Owner: ste...@…
Type: defect |Status: new
Priority: major| Milestone:
Component: coreboot |
Add support for dumping the MSRs on model_f2x and dumping GPIOs and PM
registers on ICH5.
Add ICH5 and i865 to the supported chips list.
Enable the dumping of BAR6 on i865.
Signed-off-by: Idwer Vollering vid...@gmail.com
---
Disabling memory access:
$ sudo setpci -s 6.0 0x04.b=0x0
$ sudo
I see this made it in as r6127 already.
I applied the same patch to P2B-LS and P3B-F and now my two boards
reboot and poweroff correctly too. Sweet!
I'll try to make a patch that extends this to these two boards.
Just one small detail: Actual gpo observed with oem bios for P2B-LS is
0x7fbfb9ff.
On 11/27/10 1:40 AM, repository service wrote:
+++ trunk/src/mainboard/asus/p2b/dsdt.asl Sat Nov 27 10:40:16 2010
(r6127)
@@ -0,0 +1,101 @@
...
+DefinitionBlock (DSDT.aml, DSDT, 2, CORE , COREBOOT, 1)
+{
+ /* Define the main processor.*/
+ Scope (\_PR)
+ {
+
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