[coreboot] [PATCH 2/7] SuperMicro H8SCM support (AMD SP5100)

2011-03-23 Thread Bao, Zheng
SP5100's code is based on SB700. Change the legacy sb700 of sb7xx_51xx. Signed-off-by: Zheng Bao zheng@amd.com amd_southbridge_sp5100.patch Description: amd_southbridge_sp5100.patch -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH 6/7] SuperMicro H8SCM support (SuperI/O WPCM450)

2011-03-23 Thread Bao, Zheng
This is for board Supermicro H8scm. The code was done by existing chips and superiotool. WPCM450 is more like an EC. SuperIO is just a part of multi-features. Signed-off-by: Zheng Bao zheng@amd.com superio_nuvoton_wpcm450.patch Description: superio_nuvoton_wpcm450.patch -- coreboot

[coreboot] [PATCH 3/7] SuperMicro H8SCM support (Add entries AMD SR5650 SP5100)

2011-03-23 Thread Bao, Zheng
amd_sr5650_sp5100_add_entries.patch Description: amd_sr5650_sp5100_add_entries.patch -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH 5/7] SuperMicro H8SCM support (AMD C32)

2011-03-23 Thread Bao, Zheng
Add AMD C32 support. It is based on other existing Fam10 code. Signed-off-by: Zheng Bao zheng@amd.com amd_c32.patch Description: amd_c32.patch -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH 4/7] SuperMicro H8SCM support (AMD SP5100 remove legacy)

2011-03-23 Thread Bao, Zheng
Since the SB700 has changed to sb7xx_51xx, change legacy name in other mainboard. Signed-off-by: Zheng Bao zheng@amd.com sb700_to_sb7xx_51xx.patch Description: sb700_to_sb7xx_51xx.patch -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [GSoC] Coreboot Spice Payload

2011-03-23 Thread Hao Li
Hi Leandro, Are you talking about implementing the Spice protocol client in the coreboot? Does it rely on QEMU? I think the scenario you are talking about, or Spice protocol itself, it quite similar to RDP (Remote Desktop Protocol) protocol, isn't it? In the typical client-server model, for

Re: [coreboot] [PATCH 2/7] SuperMicro H8SCM support (AMD SP5100)

2011-03-23 Thread Paul Menzel
Am Mittwoch, den 23.03.2011, 14:59 +0800 schrieb Bao, Zheng: SP5100's code is based on SB700. Change the legacy sb700 of sb7xx_51xx. Signed-off-by: Zheng Bao zheng@amd.com Index: src/southbridge/amd/sb700/Kconfig === ---

Re: [coreboot] [PATCH 4/7] SuperMicro H8SCM support (AMD SP5100 remove legacy)

2011-03-23 Thread Paul Menzel
Am Mittwoch, den 23.03.2011, 15:04 +0800 schrieb Bao, Zheng: Since the SB700 has changed to sb7xx_51xx, change legacy name in other mainboard. s/mainboard/mainboards/ Should the this patch be merged with PATCH 2/7, since otherwise the build would break in between which would prevent doing

Re: [coreboot] [PATCH 7/7] SuperMicro H8SCM support (mainboard)

2011-03-23 Thread Paul Menzel
Am Mittwoch, den 23.03.2011, 15:14 +0800 schrieb Bao, Zheng: Add support for Supermicro H8scm. It is AMD C32 + SR5650 + SP5100. Zheng, way to go! I am not knowledgeable enough to review, but thank you very much for this contribution. What H8SCM board is that? Searching for this on the WWW

Re: [coreboot] [PATCH 1/7] SuperMicro H8SCM support (AMD SR5650)

2011-03-23 Thread Alex G.
On 03/23/2011 08:56 AM, Bao, Zheng wrote: Add AMD SR56x0 support. Signed-off-by: Zheng Bao zheng@amd.com Socket C32. Thank you! Thanked-by: Alexandru Gagniuc mr.nuke...@gmail.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [GSoC] Coreboot Spice Payload

2011-03-23 Thread Leandro Dorileo
Hi Hao On Wed, Mar 23, 2011 at 3:37 AM, Hao Li li...@mprc.pku.edu.cn wrote: Hi Leandro, Are you talking about implementing the Spice protocol client in the coreboot? Yes, correct. I`m talking about implementing the Spice protocol - with that, surely I mean the client piece. Does it rely

Re: [coreboot] [GSoC] Coreboot Spice Payload

2011-03-23 Thread Hao Li
Hi Leandro, I think a simple picture describing your idea would definitely help people understand the benefit of integrating Spice into coreboot. I am not saying Spice should not be integrated into coreboot, since the coreboot's payload mechanism allows you to integrate whatever applications

Re: [coreboot] [GSoC] Coreboot Spice Payload

2011-03-23 Thread Leandro Dorileo
Hi Hao On Wed, Mar 23, 2011 at 11:28 AM, Hao Li li...@mprc.pku.edu.cn wrote: Hi Leandro, I think a simple picture describing your idea would definitely help people understand the benefit of integrating Spice into coreboot. I am not saying Spice should not be integrated into coreboot, since

[coreboot] BIOS Saviour

2011-03-23 Thread Alexandr Frolov
Hello all, I am wondering about using the BIOS Saviour device (IOSS RD1). If I understood it correctly the 'original' flash card is at the bottom and 'experimental' one is at the top. The 'original' comes with IOSS RD1 kit attached to the PLCC socket and could not be removed. The

Re: [coreboot] BIOS Saviour

2011-03-23 Thread Peter Stuge
Alexandr Frolov wrote: BIOS Saviour device .. In my board I have SST49LF080A 8 Mbit, should I use IOSS RD1-LPC8 which is 8 MBit also? Yes. The exerimental flash chip is still have to be unplugged to be reprogrammed by flash programmer. This makes sense to me only if in-circuit