SP5100's code is based on SB700. Change the legacy sb700 of sb7xx_51xx.
Signed-off-by: Zheng Bao zheng@amd.com
amd_southbridge_sp5100.patch
Description: amd_southbridge_sp5100.patch
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This is for board Supermicro H8scm. The code was done by existing chips
and
superiotool.
WPCM450 is more like an EC. SuperIO is just a part of multi-features.
Signed-off-by: Zheng Bao zheng@amd.com
superio_nuvoton_wpcm450.patch
Description: superio_nuvoton_wpcm450.patch
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coreboot
amd_sr5650_sp5100_add_entries.patch
Description: amd_sr5650_sp5100_add_entries.patch
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Add AMD C32 support.
It is based on other existing Fam10 code.
Signed-off-by: Zheng Bao zheng@amd.com
amd_c32.patch
Description: amd_c32.patch
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Since the SB700 has changed to sb7xx_51xx, change legacy name in
other mainboard.
Signed-off-by: Zheng Bao zheng@amd.com
sb700_to_sb7xx_51xx.patch
Description: sb700_to_sb7xx_51xx.patch
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Hi Leandro,
Are you talking about implementing the Spice protocol client in the
coreboot? Does it rely on QEMU? I think the scenario you are talking about,
or Spice protocol itself, it quite similar to RDP (Remote Desktop Protocol)
protocol, isn't it? In the typical client-server model, for
Am Mittwoch, den 23.03.2011, 14:59 +0800 schrieb Bao, Zheng:
SP5100's code is based on SB700. Change the legacy sb700 of
sb7xx_51xx.
Signed-off-by: Zheng Bao zheng@amd.com
Index: src/southbridge/amd/sb700/Kconfig
===
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Am Mittwoch, den 23.03.2011, 15:04 +0800 schrieb Bao, Zheng:
Since the SB700 has changed to sb7xx_51xx, change legacy name in
other mainboard.
s/mainboard/mainboards/
Should the this patch be merged with PATCH 2/7, since otherwise the
build would break in between which would prevent doing
Am Mittwoch, den 23.03.2011, 15:14 +0800 schrieb Bao, Zheng:
Add support for Supermicro H8scm.
It is AMD C32 + SR5650 + SP5100.
Zheng, way to go! I am not knowledgeable enough to review, but thank you
very much for this contribution.
What H8SCM board is that? Searching for this on the WWW
On 03/23/2011 08:56 AM, Bao, Zheng wrote:
Add AMD SR56x0 support.
Signed-off-by: Zheng Bao zheng@amd.com
Socket C32. Thank you!
Thanked-by: Alexandru Gagniuc mr.nuke...@gmail.com
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Hi Hao
On Wed, Mar 23, 2011 at 3:37 AM, Hao Li li...@mprc.pku.edu.cn wrote:
Hi Leandro,
Are you talking about implementing the Spice protocol client in the
coreboot?
Yes, correct. I`m talking about implementing the Spice protocol - with
that, surely I mean the client piece.
Does it rely
Hi Leandro,
I think a simple picture describing your idea would definitely help people
understand the benefit of integrating Spice into coreboot. I am not saying
Spice should not be integrated into coreboot, since the coreboot's payload
mechanism allows you to integrate whatever applications
Hi Hao
On Wed, Mar 23, 2011 at 11:28 AM, Hao Li li...@mprc.pku.edu.cn wrote:
Hi Leandro,
I think a simple picture describing your idea would definitely help people
understand the benefit of integrating Spice into coreboot. I am not saying
Spice should not be integrated into coreboot, since
Hello all,
I am wondering about using the BIOS Saviour device (IOSS RD1). If I
understood it correctly the 'original' flash card is at the bottom and
'experimental' one is at the top. The 'original' comes with IOSS RD1
kit attached to the PLCC socket and could not be removed. The
Alexandr Frolov wrote:
BIOS Saviour device
..
In my board I have SST49LF080A 8 Mbit, should I use IOSS RD1-LPC8
which is 8 MBit also?
Yes.
The exerimental flash chip is still have to be unplugged to be
reprogrammed by flash programmer. This makes sense to me only if
in-circuit
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