the following patch was just integrated into master:
commit 6974e425a31b1c798dd05e346e9ca4521e31079f
Author: Rudolf Marek r.ma...@assembler.cz
Date: Sat Jul 2 16:03:24 2011 +0200
Small SMM fixups
Align the spinlock to the 4 byte boundary (CPU will guarantee atomicity of
XCHG).
Ticket
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Description
#176 ste...@coresystems.de new inteltool: added PCI_DEVICE_ID_INTEL_X44 0x29e0
#174 ste...@coresystems.de new Unable to boot from qemu-kvm -- seems to be a cbfs problem
#170
Copy required SerialICE files (not patched yet), add receive byte
function to romcc_console, add SerialICE to bootblock_simple
SerialICE revision: 107
Signed-off-by: Tadas Slotkus devta...@gmail.com
---
src/arch/x86/SerialICE/io.h | 195 ++
Add serial init function example to use coreboot early serial funcions
Add selection which cpuid or msr functions to use (coreboot's or
serialice's)
Addapt for coreboot
Signed-off-by: Tadas Slotkus devta...@gmail.com
---
src/arch/x86/SerialICE/io.h|8 +++---
This is for testing/developing purpose, not for merging.
SerialICE in coreboot would be great for developing at least CPUs cache init
code.
This strategy makes use of early serial functions directly from coreboot tree.
This is with example for one board (copy from romstage early serial code for
Hello everybody,
I recently started to discover this great project you have here.
I want to play with it a bit and port it to an AMD E-350 Motherboard
(Sapphire Pure Fusion Mini E-350 - what a name...) I have at home in my
spare time.
Now I don't think that the development work is much fun, when
Hello Andreas,
Your ideas sound pretty good, but here are a couple of ideas that
might make your life easier (and cheaper).
I found some high-res pictures of your board on the web, and it looks
like that board has a footprint for a SPI programming header (labelled
SPI1, between USB1 and the SPI
Peter Stuge wrote:
you may want to look at the preliminary USB protocol document
that me and Stefan Tauner have been working on.
http://titanpad.com/x8M9ZvNeMN
//Peter
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On 7/5/11 2:25 AM, Peter Stuge wrote:
Andreas Galauner wrote:
I had the idea of developing a small Board which contains a USB port
and an SPI flash.
Sure. Or just follow Tom's tip and wire a second SPI bus master
directly onto the mainboard.
Yep, I just found the pinheader. Seems to be
Andreas Galauner wrote:
Yep, I just found the pinheader. Seems to be 1.27x1.27mm.
I also created a support ticket for the pinout on Sapphire's website.
It would be nice if they give that to me, but I really doubt it.
Did you check that it's not documented in the manual already?
I'll try to
On 7/5/11 3:02 AM, Peter Stuge wrote:
Andreas Galauner wrote:
Yep, I just found the pinheader. Seems to be 1.27x1.27mm.
I also created a support ticket for the pinout on Sapphire's website.
It would be nice if they give that to me, but I really doubt it.
Did you check that it's not
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