Am Mo 17 Okt 2011 03:24:53 CEST schrieb mopz0506 mopz0506:
coreboot is really really too hard for those users who just want
to run a NAS / BT server in his/her living room.
That's because the kind of problems that coreboot solves are hard
without some knowledge about the inner workings of
the following patch was just integrated into master:
commit 9114cfc332720cedb487c140913a45cb65b9e5e1
Author: Oskar Enoksson e...@lysator.liu.se
Date: Thu Oct 6 18:43:43 2011 +0200
Fixes several issues with amd k8 SSDT P-state generation
First issue fixed:
For multi-socket CPU
mopz0506 mopz0506 wrote:
Yes it works now.
Even though ASRock put this Always Power On feature under
SouthBridge Configuration menu item (mislead me very much),
it actually controlled by SIO, NUVOTON NCT5572D.
I think the E350M1 + coreboot is perfect for me now. so nice to
get a login:
the following patch was just integrated into master:
commit 144801207d5b1ad494d7b89b8c7156f8ae7ebd22
Author: Oskar Enoksson e...@lysator.liu.se
Date: Tue Oct 4 22:34:11 2011 +0200
Re-worked devicetree.cb for DL145 G1
After a lot of experimentation this commit improves some hardware
Noé Rubinstein (noe.rubinst...@gmail.com) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/284
-gerrit
commit 23e7b952e792935986aade22e8d84692e3714329
Author: Noe Rubinstein nrubinst...@avencall.com
Date: Tue Sep 27 14:59:12 2011 +0200
cbfstool:
Noé Rubinstein (noe.rubinst...@gmail.com) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/285
-gerrit
commit 04c13d9b86c0b2bd50f45d328cb5f914e7e13c85
Author: Noe Rubinstein nrubinst...@avencall.com
Date: Tue Oct 11 19:13:49 2011 +0200
cbfstool:
Noé Rubinstein (noe.rubinst...@gmail.com) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/286
-gerrit
commit 4d0b82fc39cf7f88be0d7a7de2e29f2377b77611
Author: Noe Rubinstein nrubinst...@avencall.com
Date: Tue Oct 11 18:27:58 2011 +0200
Document
On 10/17/2011 04:24 AM, Marc Jones wrote:
On Sun, Oct 16, 2011 at 4:57 AM, Oskar Enokssone...@lysator.liu.se wrote:
Can someone explain what RAMINIT_SYSINFO configuration option does? I
thought I understood, but I don't.
/Oskar
Hi Oskar,
RAMINIT_SYSINFO is the config option to create the
Noé Rubinstein (noe.rubinst...@gmail.com) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/286
-gerrit
commit 08bf28b8cd1179161edcedd3aedf8ce8c817d690
Author: Noe Rubinstein nrubinst...@avencall.com
Date: Tue Oct 11 18:27:58 2011 +0200
Document
Noé Rubinstein (noe.rubinst...@gmail.com) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/285
-gerrit
commit c9e030abb67122a521cf959f6feff1cf4583675c
Author: Noe Rubinstein nrubinst...@avencall.com
Date: Tue Oct 11 19:13:49 2011 +0200
cbfstool:
I doubt whether to flag this with [off-topic] because it's mostly about the
contrary of what coreboot is, but
since the issue has been commented here and awareness of it can raise
appreciation of the main
value in coreboot (freedom), I thought I'd drop two links here.
Article with FSF position
Ticket
Owner
Status
Description
#181 ste...@coresystems.de new Tyan S2885 (and other K8 boards) won't boot with TINY_BOOTBLOCK
#180 ste...@coresystems.de new ASRock E350M1 Gigabit Ethernet Problem
#179
Hi all,
I can't get serial output from the board I am trying to put coreboot on, so
I am not able to go any further to see whats going on..
The board has a Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e.
I couldn't figure out where to put the chip superio/winbond/w83627hf
section in the
the following patch was just integrated into master:
commit b11deb89f181728f75071778f22580408e74c3fd
Author: Stefan Reinauer reina...@chromium.org
Date: Fri Oct 14 12:44:14 2011 -0700
cbfstool: improve error messages
If a file can't be added by cbfstool, print the type and name of
the following patch was just integrated into master:
commit 30cb6c723bce9cac3c8e5af1b1458352d7e68002
Author: Stefan Reinauer reina...@chromium.org
Date: Fri Oct 14 15:22:52 2011 -0700
rework RTC driver output to make it more consistent.
Also add a meaningful define (Not hooked up
the superio part should placed under the LCP bridge.
for your mainboard,
it should under
device pci 1f.0 on end # LPC bridge
add the superio things like:
device pci 1f.0 on end # LPC bridge
chip superio/winbond/w83627hf
device pnp 2e.0 on #
Comments inline:
2011/10/17 Idwer Vollering vid...@gmail.com
2011/10/17 Alp Eren Köse alperenk...@buyutech.com.tr
Hi all,
I can't get serial output from the board I am trying to put coreboot on,
so I am not able to go any further to see whats going on..
The board has a Winbond
the following patch was just integrated into master:
commit 7ae18c212c2ccca0c7f4691db0bfb5c89d8ce0ac
Author: Stefan Reinauer reina...@chromium.org
Date: Fri Oct 14 15:24:03 2011 -0700
Fix our CMOS checksum algorithm so it matches what /dev/nvram expects
Our cmos checksum is
QingPei Wang wrote:
the superio part should placed under the LCP bridge.
for your mainboard,
it should under
device pci 1f.0 on end # LPC bridge
The end on this line goes after the newly introduced chip block.
add the superio things like:
device pci 1f.0 on
2011/10/17 Alp Eren Köse alperenk...@buyutech.com.tr
Hi all,
I can't get serial output from the board I am trying to put coreboot on, so
I am not able to go any further to see whats going on..
The board has a Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e.
It is likely that you need
Stefan Reinauer (stefan.reina...@coreboot.org) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/288
-gerrit
commit 699632f2925fdcb16d4dcdaed99728e29588e083
Author: Stefan Reinauer reina...@chromium.org
Date: Mon Oct 17 09:51:15 2011 -0700
Use
Stefan Reinauer (stefan.reina...@coreboot.org) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/275
-gerrit
commit d2708a3116aebba4345189ba5eb94600b7c00720
Author: Stefan Reinauer reina...@chromium.org
Date: Fri Oct 14 15:11:16 2011 -0700
Add
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/282
-gerrit
commit f8d44a08ac615fdc2ea680c187bb556e330663cc
Author: Sven Schnelle sv...@stackframe.org
Date: Sat Oct 15 17:31:01 2011 +0200
T60: Add support for
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/282
-gerrit
commit 96a5f648daea651fe427e66c62b31373a3688b38
Author: Sven Schnelle sv...@stackframe.org
Date: Sat Oct 15 17:31:01 2011 +0200
T60: Add support for
Kyösti Mälkki (kyosti.mal...@gmail.com) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/289
-gerrit
commit 598a28212e55d056e01381c017b74ef5846da3b6
Author: Kyösti Mälkki kyosti.mal...@gmail.com
Date: Sun Oct 16 18:12:59 2011 +0300
Append logical
Kyösti Mälkki (kyosti.mal...@gmail.com) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/290
-gerrit
commit 05e19920831426c5667a1fa3e856034743b1e783
Author: Kyösti Mälkki kyosti.mal...@gmail.com
Date: Mon Oct 17 17:10:03 2011 +0300
Activate older
Kyösti Mälkki (kyosti.mal...@gmail.com) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/291
-gerrit
commit 3ef8ba2d4d623e812fe8849914ebab2be22c697a
Author: Kyösti Mälkki kyosti.mal...@gmail.com
Date: Mon Oct 17 17:37:45 2011 +0300
i82801dx:
the following patch was just integrated into master:
commit 05e19920831426c5667a1fa3e856034743b1e783
Author: Kyösti Mälkki kyosti.mal...@gmail.com
Date: Mon Oct 17 17:10:03 2011 +0300
Activate older Xeon P4 microcodes
As new microcode files were included, the table was not
* Marc Jones marcj...@gmail.com [111016 10:10]:
I have created 2 devicetree file :
devicetree_f15.cb for platform with family 15 CPU
devicetree_f10.cb for platform with family 10 CPU
I changed the makefile to create a symbol link “devicetree.cb” link to
What I do is just enable the E350M1 Winbound ACPI device in devicetree.cb.
just change the off to on and everything works fine.
Is it OK to attach the patch in this mail list?
Or you can patch it for me? I don't care about that.
http://www.coreboot.org/Git requires TRUE NAME.
I'm from China
On Mon, Oct 17, 2011 at 4:40 AM, Oskar Enoksson e...@lysator.liu.se wrote:
On 10/17/2011 04:24 AM, Marc Jones wrote:
On Sun, Oct 16, 2011 at 4:57 AM, Oskar Enokssone...@lysator.liu.se
wrote:
Can someone explain what RAMINIT_SYSINFO configuration option does? I
thought I understood, but I
On Mon, Oct 17, 2011 at 4:44 PM, Stefan Reinauer
stefan.reina...@coreboot.org wrote:
* Marc Jones marcj...@gmail.com [111016 10:10]:
I have created 2 devicetree file :
devicetree_f15.cb for platform with family 15 CPU
devicetree_f10.cb for platform with family 10 CPU
I
Peter Stuge (pe...@stuge.se) just uploaded a new patch set to gerrit, which you
can find at http://review.coreboot.org/292
-gerrit
commit f2361f668a36b70c449486bfb3dfae74aefbaff7
Author: Peter Stuge pe...@stuge.se
Date: Tue Oct 18 05:10:36 2011 +0200
asrock/e350m1: Enable the superio
mopz0506 mopz0506 wrote:
What I do is just enable the E350M1 Winbound ACPI device in
devicetree.cb.
just change the off to on and everything works fine.
Aha! No code changes needed?
Is it OK to attach the patch in this mail list?
Normally everything goes via Gerrit, but because you prefer
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