Re: [coreboot] Boot flow flexibility changes

I will happily confirm you are a great mind :) ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] On loongson CPU or MIPS ARCH

Are there development systems for this CPU that we could buy to assist in the effort? Is there reference memory startup code? ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] UDELAY_IO

Question for the masses: does anyone actually use UDELAY_IO? If not, can we get rid of it? I'll prepare the patch. With APICs, HPETs, TSCs, etc I really don't see the need for such a thing. -Aaron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] UDELAY_IO

On Fri, Apr 26, 2013 at 2:29 PM, Aaron Durbin adur...@chromium.org wrote: Question for the masses: does anyone actually use UDELAY_IO? If not, can we get rid of it? I'll prepare the patch. With APICs, HPETs, TSCs, etc I really don't see the need for such a thing. Same question for

Re: [coreboot] On loongson CPU or MIPS ARCH

do we have plan to add loongson CPU or MIPS ARCH support? Loongson platforms are very different from any x86 boards. I believe that coreboot in this case would get more in the way than help. I ported GRUB to be firmware on Yeloong 2F and Fuloong 2F. Everything coreboot does on x86 including

Re: [coreboot] On loongson CPU or MIPS ARCH

I'll look at that code. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] On loongson CPU or MIPS ARCH

On 26.04.2013 23:07, ron minnich wrote: I'll look at that code. As a side note: fwstart.S inits video on yeeloong, this was done so because I was under impression that watchdog was conditioned on video init while in fact I applied wrong GPIO map. It stayed this way but doesn't have to be so.