Re: [coreboot] Windows only seeing 2GB of 4G (Seabios

But I should still see 4GB without any patch. Right? Windows only see 1.92GB as “Installed Memory (RAM)” in Control Panel->System. I am happy for the system to see up to 4GB only. From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: Tuesday, 7 June 2016 1:13 PM To: Naveed Ghori

Re: [coreboot] BSOD Win7 x86 for Baytrail E3845 Dsplay Driver

Sorry I meant v36_15_0_1091 (x86) which is the latest on the Intel website that I can find. I cannot find v36.15.0.1127. I am quite sure the driver is OK but that there is something else fundamental causing the BSOD. I have used it on another system (non coreboot) with an E3845 processor.

Re: [coreboot] Windows only seeing 2GB of 4G (Seabios

Hello Naveed, For you to read: https://en.wikipedia.org/wiki/Physical_Address_Extension Important: With PAE, IA-32 architecture is augmented with additional address lines used to select the additional memory, so physical address size increases from 32 bits

Re: [coreboot] BSOD Win7 x86 for Baytrail E3845 Dsplay Driver

Hello Naveed, Little bit of google searching: http://wikifixes.com/en/errors/0x/0xC005/?gclid=CJDYx4WIlc0CFY9uGwodBrIHbQ As I understood, you are using 36.15.0.1 (x86 aka 32b). This is very old one. The latest to use is: 36.15.0.1127 for x86 and 37.15.0.1127 for x86_64. Please, contact

[coreboot] Windows only seeing 2GB of 4G (Seabios

Hi all, I am booting a 32 bit Win 7 image (via Seabios). Windows is detecting only 1.92GB (even though there is 8GB of memory available. Being a 32 bit OS I would have expected it to see at least 4GB. Coreboot logs shows: Available memory below 4GB: 0x7ae0 (1966M) Available memory above

[coreboot] BSOD Win7 x86 for Baytrail E3845 Dsplay Driver

Hi all, I have Windows Embedded Standard 7 x86 working in with SeaBIOS. If I install the graphics driver for it however I get a BSOD while Windows is booting up (screen flashes before the BSOD) As a Coreboot newbie it would be good to get an idea as to what may cause this. I am thinking video

Re: [coreboot] PC Engines APU2 support

Hi Piotr, > Hi all, > I'm working on support for PC Engines APU2 (AMD GX-412TC) board and I > finally manage to boot Voyage Linux and run memtest86+. There some > limitations and concerns that I have and hope you can advise how to > proceed. > > 1. Platform doesn't show anything on UART after

[coreboot] PC Engines APU2 support

Hi all, I'm working on support for PC Engines APU2 (AMD GX-412TC) board and I finally manage to boot Voyage Linux and run memtest86+. There some limitations and concerns that I have and hope you can advise how to proceed. 1. Platform doesn't show anything on UART after power off. It works fine

Re: [coreboot] Discussion about dynamic PCI MMIO size on x86

On Mon, Jun 6, 2016 at 10:36 PM, ron minnich wrote: > I'm getting the sense here that reasonably modern CPUs can easily handle the > 2G hole. From what I've seen, it would not cause trouble for older CPUs > because they're most likely to be in small systems that are not likely

Re: [coreboot] Discussion about dynamic PCI MMIO size on x86

Patrick Rudolph wrote: > The easy way is to use 2G. Do this now. > The preferred way would be to mimic mrc behaviour and reboot after > finding the correct size. As Ron writes, I don't think it's neccessarily preferable to do something significantly more complex, if it isn't actually

[coreboot] UEFI project ideas

Hi all, I noticed that seabios/libpayload could have interresting use cases and I want to share/discuss them. 1) Have a SeaBIOS be a UEFI application. This would benefit on UEFI platforms without CSM. 2) Provide a minimum UEFI environment. As I noticed u-boot started to have such support. In

Re: [coreboot] Discussion about dynamic PCI MMIO size on x86

On Mon, Jun 6, 2016 at 12:52 PM Patrick Rudolph wrote: > To summarize: > The easy way is to use 2G. > The preferred way would be to mimic mrc behaviour and reboot after > finding the correct size. > > > I'm not sure it's "easy vs. preferred" so much as - simple that has no

Re: [coreboot] Discussion about dynamic PCI MMIO size on x86

To summarize: The easy way is to use 2G. The preferred way would be to mimic mrc behaviour and reboot after finding the correct size. On 2016-06-06 09:36 PM, ron minnich wrote: > I'm getting the sense here that reasonably modern CPUs can easily > handle the 2G hole. From what I've seen, it would

Re: [coreboot] Discussion about dynamic PCI MMIO size on x86

I'm getting the sense here that reasonably modern CPUs can easily handle the 2G hole. From what I've seen, it would not cause trouble for older CPUs because they're most likely to be in small systems that are not likely to have more than 2G memory anyway (I'm thinking of the vortex). The 2G hole

Re: [coreboot] autoport

Thanks Martin, I would be willing to add a command line argument to autoport for enable/disabling the glx flag passed to the inteltool if that is a preferable solution. Regards, Chris Ching On Wed, Jun 1, 2016 at 4:50 PM Martin Roth wrote: > Hi phcoder, > I'm trying to

Re: [coreboot] How to change the Core input voltage setting?

Hello Kay, I have one good advice for you. Do you have some average laptops to play with? If you do, please, install the following SW (CPU-Z) there (under WIN7/8.x/10): http://www.cpuid.com/softwares/cpu-z.html Since I am reading many email (under few identities) from you. Please, carefully

Re: [coreboot] Discussion about dynamic PCI MMIO size on x86

Hi, > I think one can go with 2GB MMIO hole. Agreeing here. We have PAE. Non-ancient 32bit kernels should support and use it, for both security reasons (nox support requires PAE page table format) and accessing physical address space above 4G. > The PCIe > 4GB is a question, I don't >

Re: [coreboot] 16GB dimm on Sandy/Ivy Bridge status

Hello Iru, Here is sku you are using: http://ark.intel.com/products/71459/Intel-Core-i7-3630QM-Processor-6M-Cache-up-to-3_40-GHz I am very sure 16MB DIMM (single memory stick) is NOT supported by MRC. Since I used to work with both IVB Emerald Lake 2 and Cougar Canyon 2 INTEL CRBs (legacy BIOS

Re: [coreboot] Discussion about dynamic PCI MMIO size on x86

Hi all, Most of 32-bit kernels (Unix/OS/whatever) usually have PAE support, so in fact they can cope with 36 bits of memory. The CPU PAE support started around Pentium. Windows XP+ has support for this. I think one can go with 2GB MMIO hole. The PCIe > 4GB is a question, I don't think