Re: [coreboot] PCI passthrough on ASUS KGPE-D16

2016-10-05 Thread taii...@gmx.com
I would really love to find a legit answer Re: what chipsets/mobos support gfx i/o fwd before I splash out hundreds of dollars. AFIAK forwarding graphics devices requires a lot more special sauce than regular pci devices (like network interfaces) On my propitiatory-firmware intel laptop

Re: [coreboot] Skylake FSP 1.1 without verstage?

2016-10-05 Thread Trammell Hudson
On Thu, Oct 06, 2016 at 01:33:53AM +0200, Zaolin wrote: > Could you please submit a bug report at ticket.coreboot.org for that issue. There seem to be two separate issues (infinite loop in romstage, fault in relocatable ramstage): https://ticket.coreboot.org/issues/77

Re: [coreboot] Skylake FSP 1.1 without verstage?

2016-10-05 Thread Aaron Durbin via coreboot
On Wed, Oct 5, 2016 at 6:25 PM, Trammell Hudson wrote: > On Wed, Oct 05, 2016 at 03:19:11PM -0500, Aaron Durbin wrote: >> On Wed, Oct 5, 2016 at 3:08 PM, Trammell Hudson wrote: >> > CBFS: 'Master Header Locator' located CBFS at [a00100:c0) >> > CBFS:

Re: [coreboot] Skylake FSP 1.1 without verstage?

2016-10-05 Thread Zaolin
Hey Trammell, congratulations ! I guess you are releasing the coreboot payload at the 33c3 ? Could you please submit a bug report at ticket.coreboot.org for that issue. Best Regards Philipp On 10/06/2016 01:25 AM, Trammell Hudson wrote: > On Wed, Oct 05, 2016 at 03:19:11PM -0500, Aaron Durbin

Re: [coreboot] Skylake FSP 1.1 without verstage?

2016-10-05 Thread Trammell Hudson
On Wed, Oct 05, 2016 at 03:19:11PM -0500, Aaron Durbin wrote: > On Wed, Oct 5, 2016 at 3:08 PM, Trammell Hudson wrote: > > CBFS: 'Master Header Locator' located CBFS at [a00100:c0) > > CBFS: Locating 'fallback/ramstage' > > CBFS: Found @ offset afc0 size 12e29 > >

Re: [coreboot] Skylake FSP 1.1 without verstage?

2016-10-05 Thread Aaron Durbin via coreboot
On Wed, Oct 5, 2016 at 3:08 PM, Trammell Hudson wrote: > On Wed, Oct 05, 2016 at 01:59:08PM -0500, Aaron Durbin wrote: >> > Does the car stage code exist somewhere else in the tree? >> >> Try this? [...] >> >> -romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S >>

Re: [coreboot] Skylake FSP 1.1 without verstage?

2016-10-05 Thread Trammell Hudson
On Wed, Oct 05, 2016 at 01:59:08PM -0500, Aaron Durbin wrote: > > Does the car stage code exist somewhere else in the tree? > > Try this? [...] > > -romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S > +romstage-y += romstage_after_verstage.S That works to make it past the

Re: [coreboot] Skylake FSP 1.1 without verstage?

2016-10-05 Thread Aaron Durbin via coreboot
On Wed, Oct 5, 2016 at 1:20 PM, Trammell Hudson wrote: > On Skylake with no verstage and FSP 1.1 there is no car_stage_entry > function, only a weak symbol with an infinite loop in > src/arch/x86/assembly_entry.S, and as a result coreboot hangs after > jumping into the romstage.

[coreboot] Skylake FSP 1.1 without verstage?

2016-10-05 Thread Trammell Hudson
On Skylake with no verstage and FSP 1.1 there is no car_stage_entry function, only a weak symbol with an infinite loop in src/arch/x86/assembly_entry.S, and as a result coreboot hangs after jumping into the romstage. There is one defined in src/soc/intel/skylake/romstage/car_stage.S, but this is

[coreboot] GPIO configuration in coreboot

2016-10-05 Thread Samuthira Pandian T
Hi Team, We need to configure two GPIO pins as output mode and toggle it in romstage(romstage.c) and ramstage (mainboard.c). Currently we are using below function calls to toggle the gpio, but it is not working. GPIO Pin Number : 59 romstage.c -- configure_score_gpio(59, PAD_FUNC0 |

Re: [coreboot] How to pass custom defined data from Coreboot to GRUB2

2016-10-05 Thread Mohan Shanmuga Sundaram
Paul, Thanks for the info! I looked into CBTABLES, but cannot understand others than CMOS table. It looks simple to me to use CMOS table that I have to define some region for user data in the 'cmos.layout' and use it at GRUB or Ubuntu Linux. But where does CMOS tables really reside? On the boot