[coreboot] Question about PCIe separate reference clock

Our VPX design uses separate reference clock source, which is Si52111-B5 (No spread), instead of common ref clock from CPU. Now The system is unstable. Reading PCIE configuration space is unstable too. (If we add some fly wire to make it work with common ref clock, the system becomes stable.)

[coreboot] REACTS Pricing Changes

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 All, We have implemented a new, flexible licensing system for our REACTS coreboot test solution. The new licensing model allows you to only pay for what you intend to use, replacing of the old fixed 5-DUT licensing system, thus lowering the barrier