Hi,
On 20.07.2017 23:48, Pavel Alyev wrote:
>
> Not at all. ME can control clock output frequency at GPIO 64/65/66/67.
> From coreboot you can only set these pins to NATIVE mode. So, if you
> EC/SIO take clock input from PCH, without ME they may work incorrectly.
you are right. I forgot that the
I hope it is in New York!
signature.asc
Description: PGP signature
--
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot
It is this the small cool machine I bought with me in Denver and showed
around.
Cherry trail seems to have made its way to a lot of cheap laptop and
tablets too (BestBuy Insignia 11' tablet)
On Sun, Jul 16, 2017 at 5:48 AM, Arne Zachlod wrote:
> Hi all,
>
> I got a GPD Pocket with an Atom X7-Z8
Not at all. ME can control clock output frequency at GPIO 64/65/66/67.
From coreboot you can only set these pins to NATIVE mode. So, if you
EC/SIO take clock input from PCH, without ME they may work incorrectly.
But looks like at t530 this outputs sets in GPIO mode. David, can you
dump gpios
To add to this, if you wish to take this task on, don't underestimate the
work involved. You can't start working on it 2 months before; a safe lead
time is 7-9 months.
You should work out the conference rooms and hotel by Jan. 1 at the latest.
Don't plan to take this on unless you're ready to do
Hello
I did the rebase in Denver. I have the same ram issues.
Unless you mean the changes have happened in the last few weeks? I have
some exams in August, I can try to rebase again in August or just send the
current patch. But it should come with a big fat warning that memory errors
do occur as
Hi David,
On 20.07.2017 18:44, David Hobach wrote:
> Dear all,
>
> just tested two coreboot + SeaBios images on a T530 that were identical
> except one time with ME and one time without (using the compile option,
> rev 54db255529ce8afc689ae425c24b7fb1d45654e8).
>
> Unfortunately it seems that ME
We are currently looking for a volunteer to host the 2018 North American
coreboot conference.
The only real requirements for the location is that it's relatively close
to a major airport and that it can hold 30-50 people comfortably. From the
feedback we got after the Denver conference, it sounds
OK, I have it working. For the Q35 qemu mainboard, I can direct SMI to the
kernel. The final issue was that the existing linux trampoline can't work
at present if you have enabled NX and set the top bit of a PTE to 1, since
the trampoline doesn't enable NX correctly. Easy fix: add nonx=off to the
c
Dear all,
just tested two coreboot + SeaBios images on a T530 that were identical
except one time with ME and one time without (using the compile option,
rev 54db255529ce8afc689ae425c24b7fb1d45654e8).
Unfortunately it seems that ME does some CPU fan initialization (ACPI?)
that coreboot doesn
Paul Kocialkowski wrote:
> I am wondering what the best way to solve this would be.
..
> * Having larger fonts for hi-dpi displays
This should be the top priority, because it provides the best user
experience. (Ie. it looks the best.)
> * Scaling the font to reach a particular DPI (e.g. based on
11 matches
Mail list logo