Hi Victor,
IMO this is really more of a feature for the Out Of Box Experience (OOBE)
rather than coreboot or seabios. If your organization uses the ChromeOS
Management Console then you should already be able to assign specific
assets to users (
src/soc/intel/broadwell/lpc.c
/* Initialize power management */
//pch_power_options(dev);
//pch_pm_init(dev);
printk(BIOS_INFO, "%s,%d.\n", __func__, __LINE__);
//pch_cg_init(dev);
printk(BIOS_INFO, "%s,%d.\n", __func__, __LINE__);
//pch_set_acpi_mode();
I need to
The ASUS KGPE-D16 fails verification for branch master as of commit
b08d73b8456c85ded8e27f37023aba27a0933031
The following tests failed:
BOOT_FAILURE
Commits since last successful test:
See attached log for details
This message was automatically generated from Raptor Engineering's ASUS
On Tue, Aug 01, 2017 at 06:47:18PM +0200, Nico Huber wrote:
> On 01.08.2017 12:13, Nico Rikken wrote:
> > Is anybody of the Coreboot community going to the SHA hacker camp the
> > coming weekend? [...]
>
> I'll be there. Though, haven't organized anything but a train ticket
> yet. You can ping me
On 01.08.2017 12:13, Nico Rikken wrote:
> Is anybody of the Coreboot community going to the SHA hacker camp the
> coming weekend? Perhaps we can meet up. I'll also bring some Coreboot-
> flashed T400's and X200 for sale.
> https://wiki.sha2017.org/w/User:Nico
I'll be there. Though, haven't
On Tue, Aug 01, 2017 at 02:49:27PM +, Peter Stuge wrote:
> Philipp Stanner wrote:
> [...]
> > * Why does every modern CPU still start in RM?
>
> Many industries run on DOS. Many system developers have created
> in-house BIOS extensions. x86 will never fully lose its 16-bit legacy.
And, just
This doesn't make sense to me. By putting the PIN in memory you expose its
value at all steps in the delivery process. Chromebooks have a very good
mechanism for keys that can be personalized to an individual, see my talk
at last year's linuxconf in berlin where I showed how you can make a
Philipp Stanner wrote:
> the more I want to contribute and learn about low-level-code the less I
> understand, it seems.
The x86 is a true rabbit hole. :)
> 2. When CB switches to PM - who generates and administrates the Page
> Tables and where?
Note that PM != paging. Neither coreboot
Hello Konstantin,
Konstantin Novikov wrote:
> Yes, now I'm using VGA port. Yes, we'll commit our changes, but after we'll
> end port. S3 isn't working now, and we have some troubles with Super I/O,
> but we already did this work with b75-port.
You don't have to wait until you have finished
Refcode is added and VGA BIOS passes.
hangs at "Set power off after power failure. "
It seems that the ME is not 100% right.
Zheng
coreboot-4.6-891-gca74434-dirty Fri Jul 28 06:45:02 UTC 2017 romstage
starting...
PM1_STS:
PM1_EN:
PM1_CNT:
TCO_STS:
Hi,
Please find the latest report on new defect(s) introduced to coreboot found
with Coverity Scan.
3 new defect(s) introduced to coreboot found with Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 3 of 3 defect(s)
** CID 1378783: Control flow issues (NO_EFFECT)
Is anybody of the Coreboot community going to the SHA hacker camp the
coming weekend? Perhaps we can meet up. I'll also bring some Coreboot-
flashed T400's and X200 for sale.
https://wiki.sha2017.org/w/User:Nico
Kind regards,
Nico Rikken (NL)
--
coreboot mailing list: coreboot@coreboot.org
12 matches
Mail list logo
