Re: [coreboot] INT 13, real mode, block write commands and coreboot

Hi, Don't worry, x86 is hard to understand IMO. I often feel like an archaeologist when trying to understand it. Am Sonntag, den 03.09.2017, 00:32 +0200 schrieb ingegneriafore...@alice.it: > is there a way to disable this BIOS function? More precisely, > coreboot can be set to avoid receiving

[coreboot] INT 13, real mode, block write commands and coreboot

Hello guys, First of all I want to thank everyone for the answers, suggestions and links you have sent me. Maybe I was wrong to ask my questions without clarifying the problem I'm analyzing, leaving you doubts about why I did some sort of questions about INT13, real mode, and so on. As you

Re: [coreboot] [flashrom] Erase failure on Sapphire Pure Platinum H61 with coreboot

Hi, On 02.09.2017 21:02, Nicola Corna wrote: > September 2, 2017 5:39 PM, "Nico Huber" wrote: >> From the original op menu these are probably unneeded: byte program >> (0x02), either one of the block erasers (0x20 and 0xd8) and the fast >> read (0x0b). >> >> Probably working (with

Re: [coreboot] REPLY: INT 13H

Philipp Stanner wrote: > As far as I understood the Intel Programmer's Manual the CPUs > provide a 16-bit compatibility-mode in 64-bit-long-mode... Every new CPU comes out of reset in 16-bit mode, just like 8086. > I don't see a reason why it should be impossible to abolish Real Mode, >

Re: [coreboot] [flashrom] Erase failure on Sapphire Pure Platinum H61 with coreboot

September 2, 2017 5:39 PM, "Nico Huber" wrote: > Hi Nicola, > > On 02.09.2017 15:06, Nicola Corna wrote: > >> Hi, >> >> I have a Sapphire Pure Platinum H61 with coreboot and flashrom fails >> to erase the flash chip (corrupting the image); attached you can find >> the log. > >

Re: [coreboot] [flashrom] Erase failure on Sapphire Pure Platinum H61 with coreboot

Hi Nicola, On 02.09.2017 15:06, Nicola Corna wrote: > Hi, > > I have a Sapphire Pure Platinum H61 with coreboot and flashrom fails > to erase the flash chip (corrupting the image); attached you can find > the log. oh, the error message is rather subtle. I'll spare you the details. The actual

Re: [coreboot] About Paging, Realmode and what is going on

Philipp Stanner wrote: > > > Why would I want to address memory in RM with 32 Bits? I don't see > > > any difference to using PM without Paging enabled. > > > > In a bootloader (after coreboot) you often want to call BIOS > > interrupt services which assume real mode, because that was the > >

Re: [coreboot] About Paging, Realmode and what is going on

Am Donnerstag, den 03.08.2017, 12:48 + schrieb Peter Stuge: > Philipp Stanner wrote: > > Why would I want to address memory in RM with 32 Bits? I don't see > > any difference to using PM without Paging enabled. > > In a bootloader (after coreboot) you often want to call BIOS > interrupt