Re: [coreboot] greetings and laptop questions

> Sorry for that. My last sentence probably doesn't even express what > I was trying to say. Could be my bad English. Your English is quite good. > I just meant that there are people who are easily offended by dishonesty. Tell me about dishonesty, Nico. What Purism does is just a pebble of sand

Re: [coreboot] Problems changing payload on Intel Leaf Hill

Hi Tahnia, Have you tried 32-bit UEFI payload? I met this problem in Denverton platfrom too with 64-bitUEFI payload. Thanks. Regards, Melissa Yi BIOS Lead Engineer Celestica(Shanghai) R Center, China www.celestica.com Solid Partners, Flexible Solutions 2017-10-10 16:29 GMT+08:00 Tahnia

Re: [coreboot] greetings and laptop questions

Thanks for all the interesting information for my questions (and - um - "commentary" :-) It has given me a lot to think about. Best, Jim On Tue, Oct 10, 2017 at 7:10 PM, taii...@gmx.com wrote: > The lenovo G505S is the latest owner controlled coreboot x86-64 laptop, >

[coreboot] Freedom Inside - certification system

In addition to the existing FSF RYF system I propose the creation of a "Freedom Inside" rating and certification system where vendors (now that there are more than a few) can have their products certified by a central body. This would have: Multiple levels of freedom with a clear central

Re: [coreboot] greetings and laptop questions

The lenovo G505S is the latest owner controlled coreboot x86-64 laptop, running the FT3 platform which is 4 years old. It supports VMX, RVI and IOMMU. While it does have a blob for video and power both of those have no hardware code signing features (thus replaceable), and unlike ivy bridge

Re: [coreboot] greetings and laptop questions

On 10.10.2017 20:02, Youness Alaoui wrote: >> So my conclusion, Purism draws customers from other Linux supporting >> vendors with dishonest marketing. If that doesn't bother you, fine. >> But please don't get angry if it bothers honest people. > > ... > 3 - By stating that it "bothers honest

Re: [coreboot] greetings and laptop questions

I actually appreciated your super-long post, as it provided me insight in the development process that I wasn't aware prior and it changed my view on Puri.sm from 'they have been debunked' to 'I want to support their efforts'. Keep up the good work. On Tue, Oct 10, 2017 at 2:02 PM, Youness Alaoui

Re: [coreboot] greetings and laptop questions

> While I understand your frustration, and agree with the general thrust > of your email, and disregarding the "10 years", the Samsung Chromebook > Plus (and many other devices of similar age) beg to differ. > There are devices from 2016 and 2017 shipping with coreboot and no CPU > level blobs in

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

> Last time I was solving a problem of OS suspend-resume sequence with modern kernels and now it is about working with old kernels Hello Kostja, What is modern kernel, and what is old kernel? Any version/revision examples (you are using), so we can get the/some idea? Thank you, Zoran ___

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

> I'm going to try the hack to disable xhci, as suggested by Zoran and Аладышев's earlier email. You might try both variants. Do not forget, both ehci and xhci hubs are on different clocking domains, so you can set only one at the time (no workaround/circumventing tricks). I would advise to try

Re: [coreboot] OCP Winterfell, NERF, Linux and u-root (was: Ability to remotely debug the grub menu in case of boot failure)

Here's a bit more info. NERF is the project I mentioned at the coreboot meeting a few months back. This is my linuxcon talk a few weeks back. https://docs.google.com/presentation/d/1rz6ATJ6PNf_iJeDlqJvLqYZmyuJIN5SMli8halvyovY/edit?usp=sharing HOWTO on the winterfell node, incomplete:

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

On Tue, Oct 10, 2017 at 02:44:02PM +, ron minnich wrote: > [0.376881] ACPI Error: Hardware did not enter ACPI mode > (20160831/evxfevnt-113) > > is this the step where it tries to do an outb to 0xb2 to tell smm we are > taking over? Yes, it looks like it is attempting to write to 0xB2:

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

[0.376881] ACPI Error: Hardware did not enter ACPI mode (20160831/evxfevnt-113) is this the step where it tries to do an outb to 0xb2 to tell smm we are taking over? -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Problems changing payload on Intel Leaf Hill

Hi Tahnia, On 10.10.2017 10:29, Tahnia Lichtenstein wrote: > ... > > Then I built this version of coreboot with a self-compiled payload, such as > Tianocore UDK2017 CorebootPayloadPkg or SeaBIOS, using the .confg files > provided by Intel for UEFI payloads or legacy payloads respectively (just >

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

On Mon, Oct 09, 2017 at 07:55:34PM -0700, Julius Werner wrote: > My gut feeling would be to blame ACPI. The Linux patch is about > caching a host controller register in the kernel, and in some cases > (e.g. ehci_reset()), the patch re-reads the cached version from the > hardware whereas the

Re: [coreboot] ECC2017: organized dinner on Thursday?

Hey, I have already organized the Dinner for Thursday and Friday. ;) Best Regards, Philipp On 10.10.2017 10:46, Goetz Salzmann wrote: > Dear list, > > looking at the ECC2017 Schedule there is an organized "Social Event" on > Friday. For Sat./Sun. we will probably have pizza in the hackcenter.

Re: [coreboot] how to implement variable read/write variable in coreboot

Hi Nico! I'm not sure how to use a per erase-block counter? When would it update? we could only do that on every erase. A per variable counter might be useful, but I still hope it will work without. I was thinking of putting a number in the first word of a block. Every time a new block is

[coreboot] ECC2017: organized dinner on Thursday?

Dear list, looking at the ECC2017 Schedule there is an organized "Social Event" on Friday. For Sat./Sun. we will probably have pizza in the hackcenter. But after the great experience with organized dinners during the EuroBSDCon 2017, I would like to ask someone from Bochum to organize a dinner

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

Hello Zoran! Yes, I'm working with the same board, but the problem is different. Last time I was solving a problem of OS suspend-resume sequence with modern kernels and now it is about working with old kernels From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: Tuesday,

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

I've dumped original ACPI tables from original BIOS, but I can't see any such hooks. https://pastebin.com/Mniskv3f part1 of dsdt https://pastebin.com/hnpgvCMN part2 of dsdt (starts from EHCI/XHCI controllers) I hope it is not in SMM cause I really have no idea how to edit it to solve

Re: [coreboot] greetings and laptop questions

Hi Youness, 2017-10-10 1:54 GMT+02:00 Youness Alaoui : > it uses FSP, but you fail to mention that anything using coreboot will > use the FSP unless it's 10 year old hardware (Sandybridge is the > latest FSP-free supported CPU). While I understand your

Re: [coreboot] how to implement variable read/write variable in coreboot

Thank you very much for all your advice, especially for Nico, Felix, Peter Thanks. Regards, Melissa Yi BIOS Lead Engineer Celestica(Shanghai) R Center, China www.celestica.com Solid Partners, Flexible Solutions 2017-10-02 4:22 GMT+08:00 Felix Held : > Hi Nico! >

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

Hello Kostja, We already had this discussion a while ago, didn't we? https://mail.coreboot.org/pipermail/coreboot/2016-December/082772.html (BTW, ATOM BYT has exactly the same problem) Zoran On Mon, Oct 9, 2017 at 11:58 AM, Аладышев Константин wrote: > I try to port