Re: [coreboot] BayTrail PCIe problems (hangup) in FSP (in U-Boot)

Hi Stefan, we have two versions in the tree a) fsp baytrail b) non-fsp baytrail but with mrc.bin as meminit Do you tried to use coreboot (w/o FSP) + u-boot instead? Or is this out of scope? Best, lynxis -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221

Re: [coreboot] KGPE-D16 AMD-vi fails because combined sata is enabled

As I understand the code, KGPE-d16 doesn't use AGESA part (nor any?). Any reason why this value would be defaulting to enabled for whole sb700 dependents? --- a/src/vendorcode/amd/cimx/sb700/SBTYPE.h +++ b/src/vendorcode/amd/cimx/sb700/SBTYPE.h @@ -133,7 +133,7 @@ typedef struct _AMDSBCFG

Re: [coreboot] X230 coreboot potential issues?

Hello Hans, On 27.10.2017 22:10, Hans Fritz wrote: > Hi, I installed coreboot on my X230, > it works very well Would you mind sharing the configuration setting you have chosen? I am still struggling getting a good Coreboot Config for my X230 which will support Linux and Windows (SeaBIOS).

Re: [coreboot] [VERY IMPORTANT] Announcement regarding Apollo Lake Coreboot building

Zoran, and others, I wanted to build coreboot for APL CRP too. Tried to compile but failed at last command I think. *Image written successfully to build/cbfs/fallback/ifwi.bin.tmp.* *INFO: Performing operation on 'IFWI' region...* *E: Image is missing 'IFWI' region* *E: The image will

Re: [coreboot] X230 coreboot potential issues?

Hi, On 27.10.2017 22:10, Hans Fritz wrote: Hi, I installed coreboot on my X230, it works very well except for these two things: When the screen goes to sleep and I move the mouse to wake it up, it wakes up at full brightness regardless of what the setting was before it went to sleep. If I

Re: [coreboot] Does S3 work on Haswell boards?

On Thu, Nov 2, 2017 at 1:48 PM, Nico Huber wrote: > Hi Aladyshev, > > On 30.10.2017 16:49, Аладышев Константин wrote: > >> Does S3 work on Haswell boards? >> > > It definitely worked at some point. Matt might know a latest revision > where it was tested on Chromebooks or maybe can

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

Hi, On 27.10.2017 14:14, Аладышев Константин wrote: Ok, I’ve found one more solution: don’t generate ACPI C-state tables. the possible workarounds all seem very unrelated to me. There is a high chance that your outdated kernels contain too much undefined behaviour and the only thing you

Re: [coreboot] Does S3 work on Haswell boards?

Hi Aladyshev, On 30.10.2017 16:49, Аладышев Константин wrote: I have problem with S3 mode on Haswell board. Everything is fine if S3 time is very small (<15 seconds), but if it is longer, coreboot won't resume. It fails on quick_ram_check. sounds much like the DRAM loses some state. e.g. if

Re: [coreboot] New bugtracker/wiki registration process - please do not use freenode irc servers

First: We want to make the registration progress more simple and fast. Have you read the broken (later more about that) howto you have posted? Tor users should not have to do anything more of work then regular users do. Otherwise it would be a discrimination of people who support tor. Its of

Re: [coreboot] New bugtracker/wiki registration process - please do not use freenode irc servers

Thanks for your note. Please then run few tor exit nodes after you checked the law in your country to help the network. > > Those people are providing great diversity for having a non centralized TOR > > network. > > In sincere hope that TOR network will change (for the much better) state of

Re: [coreboot] BayTrail PCIe problems (hangup) in FSP (in U-Boot)

On Thu, Nov 2, 2017 at 8:44 AM Stefan Roese wrote: > > > In this special case, I might have triggered a bug / issue in the Intel > FSP and solving this might also help the coreboot project / community. > > > Sounds good to me. I have no complaint with what you're doing; the more

Re: [coreboot] BayTrail PCIe problems (hangup) in FSP (in U-Boot)

Hi Ron, On 02.11.2017 16:20, ron minnich wrote: Simon Glass has done excellent work with making u-boot run as a coreboot payload for at least 5 years now. You might want to talk to him. It might help avoid a lot of unnecessary work. Just a thought. I'm in contact with Simon, thanks for the

Re: [coreboot] BayTrail PCIe problems (hangup) in FSP (in U-Boot)

Simon Glass has done excellent work with making u-boot run as a coreboot payload for at least 5 years now. You might want to talk to him. It might help avoid a lot of unnecessary work. Just a thought. On Thu, Nov 2, 2017 at 7:31 AM Peter Stuge wrote: > Hi Stefan, > > Stefan

Re: [coreboot] BayTrail PCIe problems (hangup) in FSP (in U-Boot)

Hi Stefan, Stefan Roese wrote: > I'm facing a PCIe init related problem most likely caused in the > Intel FSP in our BayTrail U-Boot port (not coreboot!). I hope you > don't mind me posting this question on this coreboot list, since > here many more people are present with Intel FSP knowledge. I

Re: [coreboot] New bugtracker/wiki registration process - please do not use freenode irc servers

ng0 transcribed 3.7K bytes: > Peter Stuge transcribed 1.3K bytes: > > dz6g...@tuta.io wrote: > > > But please dont use freenode irc or any other IRC server that are > > > blocking TOR users. > > .. > > > Net neutrality is important. Please dont move coreboot into the > > > situation that you cant

Re: [coreboot] New bugtracker/wiki registration process - please do not use freenode irc servers

Am Do., 2. Nov. 2017 um 14:14 Uhr schrieb Peter Stuge : > Wiki admins: Would that need more effort than IRC integration? > JFYI: This thread is the first time I hear about such ideas, and I kinda administrate the wiki. So there's that. Patrick -- Google Germany GmbH, ABC-Str.

[coreboot] BayTrail PCIe problems (hangup) in FSP (in U-Boot)

Hi, I'm facing a PCIe init related problem most likely caused in the Intel FSP in our BayTrail U-Boot port (not coreboot!). I hope you don't mind me posting this question on this coreboot list, since here many more people are present with Intel FSP knowledge. So here we go: We are currently

Re: [coreboot] New bugtracker/wiki registration process - please do not use freenode irc servers

Peter Stuge transcribed 1.3K bytes: > dz6g...@tuta.io wrote: > > But please dont use freenode irc or any other IRC server that are > > blocking TOR users. > .. > > Net neutrality is important. Please dont move coreboot into the > > situation that you cant register because of broken net neutrality.

Re: [coreboot] KGPE-D16 AMD-vi fails because combined sata is enabled

Thierry Laurion wrote: > ENABLE_IDE_COMBINED_MODE available for sp800 but not for sp700, for ewhich > sp5100 is derived from: .. > Suggested Workaround > Disable combined mode by setting a platform BIOS callback option to CIMx > called "SataIdeCombinedMode" to 0. .. > Is there something i'm

Re: [coreboot] New bugtracker/wiki registration process - please do not use freenode irc servers

dz6g...@tuta.io wrote: > But please dont use freenode irc or any other IRC server that are > blocking TOR users. .. > Net neutrality is important. Please dont move coreboot into the > situation that you cant register because of broken net neutrality. This is a good point, thanks for bringing it

Re: [coreboot] Coreboot support on H8SGL-F

On 11/02/2017 01:36 AM, taii...@gmx.com wrote: > On 11/01/2017 08:06 AM, Lucian Cojocar wrote: > >> Hi, >> >> Is coreboot working on the H8SGL-F motherboard[1] with AMD Opteron 6168 >> (10h Family)? > Probably not, the code hasn't been modified since 2011. > > I would just get a KGPE-D16, then

Re: [coreboot] Problems changing payload on Intel Leaf Hill

Hi Kevin, Yes, we had to make another adjustment. I think SeaBios is expecting a pointer at this position to the beginning of the CBFS. But coreboot doesn't enter anything there, because everything works over the FMAP. But it may also be that we are still doing something wrong. ->