Re: [coreboot] Problems changing payload on Intel Leaf Hill

Hi Mario, I have built my coreboot.rom now but still having problem booting it up (see black screen on monitor). I am not sure few of these settings in my .config is correct or not:- CONFIG_VGA_BIOS_ID="1106,3230" (how to know and confirm this is my ID? is this important?)

Re: [coreboot] Problems changing payload on Intel Leaf Hill

Hi Mario, I have built my coreboot.rom now but still having problem booting it up (see black screen on monitor). I am not sure few of these settings in my .config is correct or not:- CONFIG_VGA_BIOS_ID="1106,3230" (how to know and confirm this is my ID? is this important?)

Re: [coreboot] AMG G-series - Steppe eagle - PCI IRQ Routing to 8259 PIC

Hi Abhishek, Please can you check if you programmed the ELCR registers 0x4d0/0x4d1 to level for PCI registers? In other words, you should set bits to 1 to corresponding IRQ to be level triggered. Eg. for IRQ 5, you need to write 1 to bit5 to 8bit I/O port 0x4d0 For IRQ 9, you need to program bit

Re: [coreboot] IOMMU/PCI passthrough on the PCENGINES APU2 board

-BEGIN PGP SIGNED MESSAGE- Hash: SHA512 On 11/02/2017 04:22 PM, Christoph Pomaska wrote: > Hi, Hi Christoph, > I am currently trying to get IOMMU on the APU2 board to work and > found this commit: https://review.coreboot.org/#/c/15165/ > > What is the current state of that code?

[coreboot] AMG G-series - Steppe eagle - PCI IRQ Routing to 8259 PIC

Hi, I am facing an issue routing the interrupts from the Ethernet devices which are on GPP PCIe 1, GPP PCIe 2, and GPP PCIe 3 on a custom hardware that is running AMD G-series - Steppe eagle (Mullins, Family 16h Model 30h-3Fh) . I am attempting to use the PCI IRQ from the Ethernet devices, but

Re: [coreboot] BayTrail PCIe problems (hangup) in FSP (in U-Boot)

Hallo Zoran, In message you wrote: > > Let us involve in this discussion Mr Denk (father of U-Boot, I know Mr Denk > personally)), and Mr Glass (option [B] here mentioned below)... For the > (targeted by me) purposes (History

[coreboot] IOMMU/PCI passthrough on the PCENGINES APU2 board

Hi, I am currently trying to get IOMMU on the APU2 board to work and found this commit: https://review.coreboot.org/#/c/15165/ What is the current state of that code? (Seems like there is need of an update regarding the added variants of the board to the master tree) Is there still being

Re: [coreboot] KGPE-D16 AMD-vi fails because combined sata is enabled

Thank you for the clarification. I'll try to figure this out later this week. Any help would be appreciated. I suppose I should file an issue. Will do. Le ven. 3 nov. 2017 04:19, Patrick Georgi a écrit : > That's the bitfield item's size field, not its default value. > > >