Re: [coreboot] Coreboot Purism BIOS is free? open?

On 12/18/2017 01:59 PM, Youness Alaoui wrote: As for Taiidan's response, I think Matt's response to it is pretty good already, and I'm tired of seeing Taiidan jumping at the chance to talk against Purism every chance he gets I simply want people to have all the facts before they spend thousands

Re: [coreboot] Coreboot Purism BIOS is free? open?

THANKS KAKAROTO!! I alredy have fun! If my head does not explode and my laptop does not explode, I'll write you soon hahahaha 2017-12-19 21:54 GMT+01:00 Timothy Pearson : > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA1 > > Thank you for the detailed

Re: [coreboot] Coreboot Purism BIOS is free? open?

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Thank you for the detailed explanation. I guess this is an area in which experience matters; it is absolutely unacceptable (and not unexpected) that Intel misled your CEO, but this is sadly not an uncommon tactic in the industry. One item I would

Re: [coreboot] Coreboot Purism BIOS is free? open?

On Tue, Dec 19, 2017 at 2:07 PM, Timothy Pearson wrote: > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA1 > > On 12/19/2017 11:51 AM, Dame Más wrote: >> I finished the University and I have free time to do things. And this >> seems like an interesting project to

Re: [coreboot] Coreboot Purism BIOS is free? open?

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 12/19/2017 11:51 AM, Dame Más wrote: > I finished the University and I have free time to do things. And this > seems like an interesting project to which I dedicate many hours. > > The truth is that I read a lot these days. The work you do

Re: [coreboot] Depthcharge License

To be fair, it appears that many source files refer to a non-existent LICENSE file. Someone on the CrOS team should probably just add the LICENSE file for depthcharge and/or contact mal@ to see how the license info is being collected these days (e.g. for chrome://os-credits

Re: [coreboot] Coreboot Purism BIOS is free? open?

I finished the University and I have free time to do things. And this seems like an interesting project to which I dedicate many hours. The truth is that I read a lot these days. The work you do kakaroto is impressive. In general Purism is doing something big, and I spoke ahead of time. I saw

Re: [coreboot] Depthcharge License

Is there even a question? Looks like aaron just answered the original question, which boils down to Read The Source? On Tue, Dec 19, 2017 at 7:58 AM Aaron Durbin via coreboot < coreboot@coreboot.org> wrote: > On Tue, Dec 19, 2017 at 8:03 AM, wrote: > >> On 2017-12-15

[coreboot] New Defects reported by Coverity Scan for coreboot

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s)

Re: [coreboot] Depthcharge License

On Tue, Dec 19, 2017 at 8:03 AM, wrote: > On 2017-12-15 13:39, ttu...@codeaurora.org wrote: > >> Preparing to mirror the coreboot.org requires us to vet the various >> licenses, etc. >> >> There doesn't appear to be a LICENSE or COPYING file in the Depthcharge >> tree. >>

Re: [coreboot] Depthcharge License

On 2017-12-15 13:39, ttu...@codeaurora.org wrote: Preparing to mirror the coreboot.org requires us to vet the various licenses, etc. There doesn't appear to be a LICENSE or COPYING file in the Depthcharge tree. My understanding is that Depthcharge is licensed GPLv2 (or later). How would I

Re: [coreboot] Coreboot Purism BIOS is free? open?

Hi, On 18.12.2017 10:07, Dame Más wrote: Hello, I understand. I want implement Coreboot for current 7th and 8th generation Intel computers. coreboot already works on 7th gen Intel (Kaby Lake). Not sure what 8th gen generally refers to. Kaby Lake Refresh might work as well, and Cannon Lake is

Re: [coreboot] Early debugging

I have made some progress since yesterday and now I have much better results: * Adding a setting to romstage to disable PCI-PCI bridge and enabling its pins as GPIO (that's what the datasheet says) made it possible to initialize the PCIe bridge @00:02.1. * Adding the base address 0x0 to unused