Re: [coreboot] HP Elitebook 8770w Suspend-to-RAM

I merely downgraded to 1.10.3.On Jan 13, 2018 6:42 AM, Nico Huber wrote: > > On 12.01.2018 00:57, Robert Reeves wrote: > > Yep, looks like that was the problem. I'm glad it was something simple. Thanks. > > So did you fix it? or only work around? as many people run into trouble > lately with

Re: [coreboot] Missing PCIe devices

Hi On Sat, Jan 13, 2018 at 8:51 PM, Hal Martin wrote: > Hi all, > > Is there any documentation around describing how coreboot scans for PCI > Express buses and devices? Don't know of one. It's a recursive walk of the PCI tree, with the assigned bus number incremented for

[coreboot] Missing PCIe devices

Hi all, Is there any documentation around describing how coreboot scans for PCI Express buses and devices? I have an expansion module for the Intense PC I'd like to get working with Coreboot. The expansion module adds 4 Intel Gigabit Ethernet interfaces (82574L) via PCI Express 4 PCIe ports. All

Re: [coreboot] Disabling hyper-threading on Ivy Bridge

Thanks Nico, this info is very helpful. I now know where to start reading. Best regards, Davíð On Sat, Jan 13, 2018 at 05:13:01PM +0100, Nico Huber wrote: > Hi Davíð, > > On 13.01.2018 15:34, Davíð Steinn Geirsson wrote: > > I am hoping to build coreboot with hyper-threading (SMT) disabled. I >

Re: [coreboot] Disabling hyper-threading on Ivy Bridge

On 13.01.2018 17:13, Nico Huber wrote: You can check if hyper-threading is enabled by looking at MSR 0x35 (CORE_THREAD_COUNT) or CPUID (eax 0x0b, ecx 0x00 / 0x01). Both should be documented in Intel's SDM [1]. Forgot the link: [1] https://software.intel.com/en-us/articles/intel-sdm --

Re: [coreboot] Disabling hyper-threading on Ivy Bridge

Hi Davíð, On 13.01.2018 15:34, Davíð Steinn Geirsson wrote: I am hoping to build coreboot with hyper-threading (SMT) disabled. I guess this can be done by skipping over the right processor IDs in the for loop in intel_cores_init in src/cpu/intel/model_206ax/model_206ax_init.c:470 ? no, you

[coreboot] Disabling hyper-threading on Ivy Bridge

Hi all, Can someone advise on how logical/physical processors are numbered for Ivy Bridge CPUs? I am hoping to build coreboot with hyper-threading (SMT) disabled. I guess this can be done by skipping over the right processor IDs in the for loop in intel_cores_init in

Re: [coreboot] HP Elitebook 8770w Suspend-to-RAM

On 12.01.2018 00:57, Robert Reeves wrote: > Yep, looks like that was the problem. I'm glad it was something simple. > Thanks. So did you fix it? or only work around? as many people run into trouble lately with the coreboot + SeaBIOS combination, I'm curious about what's causing the trouble.