Re: [coreboot] L1TF

2018-08-15 Thread Rudolf Marek
Hi, On 15.8.2018 15:58, Shawn wrote: According to the vulnerability analysis, the SMM is affected by L1TF. Since SMM code base in coreboot is much smaller than OEM's firmware, IMOHO L1TF is not practical on coreboot. Any idea about is coreboot vulnerable to L1TF? You need an updated microcode, s

[coreboot] Build fails on Thinkpad W520

2018-08-15 Thread Andreas Restle
Building coreboot for Thinkpad W520 currently fails with the following error: CC romstage/northbridge/intel/sandybridge/raminit_common.o In file included from src/northbridge/intel/sandybridge/raminit_common.c:18: src/northbridge/intel/sandybridge/raminit_common.c: In function 'dram_od

Re: [coreboot] Building an image a second/third/... time fails

2018-08-15 Thread Nico Huber
On 14.08.2018 12:49, h...@memeware.net wrote: > I had build once a coreboot image for a Intel G41 board. Then i liked to > build for an other Intel G41 board. It looks like you either used an older IASL for this initial build or chose a different SeaBIOS version. Nico > I first removed the confi

Re: [coreboot] Intel G41 - Asrock G41M-GS: no coreboot screen output from Intel GPU on VGA

2018-08-15 Thread Nico Huber
Hi, On 14.08.2018 13:41, h...@memeware.net wrote: > So it seems to have detected that my screen is 1920*1080. GPU + screen > detection seems to be working. But i dont get any coreboot output on the > screen. you can set CONFIG_DEBUG_ADA_CODE to enable verbose messages in libgfxinit. At least this

[coreboot] L1TF

2018-08-15 Thread Shawn
Hi guys, Some of you might already noticed the new side-channel attack called L1 Terminal Fault is made public late: https://software.intel.com/security-software-guidance/software-guidance/l1-terminal-fault https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-l1

Re: [coreboot] Intel G41 - Asrock G41M-GS: no coreboot screen output from Intel GPU on VGA

2018-08-15 Thread h42
Its not a slow reacting monitor. I already pressed it blind before reporting the issue here without any success. Its a modern, fast reacting LED monitor (ccfl takes longer to turn on). I get immediately after powering on a coreboot screen on the monitor when i insert a PCIe graphics card into

Re: [coreboot] Build failure, build log dont link in a proper way

2018-08-15 Thread Nico Huber
Hi, On 14.08.2018 12:08, h...@memeware.net wrote: > I cloned today the fresh code on a new machine. I first installed the > dependencies listed here https://www.coreboot.org/Build_HOWTO and then i > liked to build the whole build gcc for all platforms. I ran 'make > crossgcc CPUS=6' in the fresh c