Solved. Not know why.
set IoapicSbFeatureEn=1.
Zheng
From: Rudolf Marek
Sent: Friday, October 26, 2018 8:06 PM
To: Zheng Bao; coreboot@coreboot.org
Subject: Re: [coreboot] [AMD family16h] What need to be done in coreboot to
support the Virtual Wire mode
Hi,
Hi,
Please find the latest report on new defect(s) introduced to coreboot found
with Coverity Scan.
2 new defect(s) introduced to coreboot found with Coverity Scan.
3 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent
build analyzed by Coverity Scan.
New defect(s)
Hi,
Dne 25. 10. 18 v 9:17 Zheng Bao napsal(a):
> Any more ideas? Thanks.
Maybe the bus topology is different in coreboot. It would explain why SATA
works, because it is on bus 0.
Thanks,
Rudolf
--
coreboot mailing list: coreboot@coreboot.org
I suggest you better check
1. power on sequence,
2. every power/ voltage rail stability during boot process.
3. Over/undershoot.
4. all crystal osc frequency stability during boot process.
5. Try to print the DID early during bootblock and romstage.
Provide your observations.
Regards,
Naresh G
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