Hi fellow engineers,
I got that RAM stick working when I changed the fourth byte of SPD from from
mini-UDIMM (0x06) to SO-DIMM (0x03) and its working fine... But still I am
curious why mini-UDIMM didn't work out. Perhaps this form factor was not
supported by FSP?
Another thing I observed that
I want to update the boot firmware used by an "ancient" ISA bus PC that I'm
trying to reactivate. Kevin O'C. told me to use SeaBIOS, I need to use
Coreboot. So, here I am.
FWIW, I'm a retired IBM mainframe system programmer, with more than 45 years of
experience. Please be very gentle with
On Wed, Nov 06, 2019 at 12:39:59PM +0100, Nico Huber wrote:
> > Some of the mega patches are copies of a predecessor chip (with the
> > minimum amount of changes to integrate it in the build), that are
> > then modified to fit the new chip.
>
> Ack. I think that is a problem. If this procedure is
Hi all,
I've built a coreboot with the LinuxBoot payload. The kernel is the stable
5.3.8 version and the intiramfs is the u-root master version.
All with the default choices. I'm using coreboot 4.10.
Once the system boots I get a framebuffer console without usb keyboard support
and the u-root
Am 05.11.19 um 20:23 schrieb Patrick Georgi:
> On Tue, Nov 05, 2019 at 06:37:02PM +0100, Nico Huber wrote:
>> I mean "rubber-stamping of *huge* commits". That huge that it is
>> obvious that no review happened, e.g. 1k+ LOC copy-pasta. Also, the
>> guidelines say "This means you shouldn't +2 a
Please ignore the addendum (that was my own repo messed up, found the
smi_handler at src/soc/intel/fsp_broadwell_de/smihandler.c).
Please consider the first message.
Regards,
Naveen
From: Naveen Chaudhary
Sent: Wednesday, November 6, 2019 2:06 PM
To:
Addendum :
Looks like i referred to some different code version:
https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/firmware-link-2695.B/src/cpu/x86/smm/smihandler.c
There is no such nmi_handler in coreboot. So the previous questions are now
even more important.
Regards,
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