Hello,
I own a Thinkpad X230t and I encountered Coreboot project on the Internet. I
enjoy FOSS stuff, and also I would like to change my WWAN/WLAN cards in my
computer so I decided to switch from proprietary Lenovo UEFI firmware to
Coreboot. By the way I found that those Thinkpads are well
Hi Persmule,
On Thu, Jul 16, 2020 at 5:17 PM Persmule wrote:
>
> Hi Angel Pons,
>
> It seems that we may copy ec/lenovo/h8 to ec/lenovo/mec16xx ( or separate
> directory for different chips ) to start dedicated support to them, since
> though they are different, their behavior are so similar
Hi Angel Pons,
It seems that we may copy ec/lenovo/h8 to ec/lenovo/mec16xx ( or separate
directory for different chips ) to start dedicated support to them, since
though they are different, their behavior are so similar that code for
ec/lenovo/h8 can work on them, though buggy.
Best regards,
Hi Persmule,
On Thu, Jul 16, 2020 at 5:02 PM Persmule wrote:
>
> Hi Angel Pons,
>
> ‐‐‐ Original Message ‐‐‐
> On Thursday, July 16, 2020 2:47 PM, Angel Pons wrote:
> > I suspect that reusing the H8 EC code for the xx30 series Thinkpads is
> > a source of bugs. There isn't any H8 EC on
Hi Angel Pons,
‐‐‐ Original Message ‐‐‐
On Thursday, July 16, 2020 2:47 PM, Angel Pons wrote:
>
> I suspect that reusing the H8 EC code for the xx30 series Thinkpads is
> a source of bugs. There isn't any H8 EC on those mainboards anymore,
> the EC was replaced with a completely
Hi Persmule,
I don't own any Thinkpads so I can't test anything. Still, here's my
two cents about the issue at hand.
On Thu, Jul 16, 2020 at 1:43 PM Persmule wrote:
>
> Hi all,
> Days ago the coreboot port for Thinkpad X230s (
> https://review.coreboot.org/c/coreboot/+/41390 ) for one of my
Hi all,
Days ago the coreboot port for Thinkpad X230s (
https://review.coreboot.org/c/coreboot/+/41390 ) for one of my friends got
merged. Most stuffs on this laptop proves to work fine, but the interaction
between its EC and cellular modem installed in its internal M.2 socket is
detected to
Hi Angel,
here are the read outs (-X -0) for the MSRs:
0x00CE -> 00080C10F0011C00
0x0194 -> 0009
0x01AD -> 24242526
I'd say the issue is because of how I determine the overclocking
headroom that the CPU is capable of. On my CPUs, it happens that the
number of
A new post titled "[GSoC] Address Sanitizer, Part 1" has been published on the coreboot blog. Find the full post at https://blogs.coreboot.org/blog/2020/07/16/gsoc-address-sanitizer-part-1/
Hello everyone. My name is Harshit Sharma (hst on IRC). I am working on the project to add the “Address
Dear Vivek,
Am 16.07.20 um 00:46 schrieb Vivek Gupta via coreboot:
I am currently looking to setup AARCH64 platform simulation
verification of coreboot on Gem5 simulation environment. Do we have
any document/wikipage to understand the compilation and configuration
process?
The tutorial [1]
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