The factory BIOS is write protected with that efi module. To have an
unrestricted factory firmware, your options are:
- dump the chip, remove the module and reflash the content
- remove the module from the image you want to flash, and flash it with EZflash
This module exists in the factory BIOS for
>
> if the AmdSpiRomProtect modules have been deleted in the factory image
> previously.
> So what does that mean? How can i do that? I would like to flash it
> internal
I don't recognize the "AmdSpiRomProtect modules". My top guess, though, is
it's referring to something that would program the
maybe Balazs could advise. However, to make sure you could easily
unbrick your A88XM-E in the case of a bad coreboot build, I really
recommend you to order a cheap USB CH341A programmer (preferably with
a Green PCB) - and PLCC clip to easily remove a DIP8 flash chip from a
motherboard's socket with
Michal Zygowski wrote:
> I don't think it is necessary to port IDS to Kconfig.
I have an old branch where I started doing just that. I think I
posted some patches but there was no traction. At that time I think
it was still uncertain if we would ever receive any AGESA support
from AMD, so there wa
Of course it is reachable. Here's the license:
https://www.coreboot.org/Logo#coreboot_Logo_License
On 16.10.2020 17:46, Peter Stuge wrote:
> Vegetable Lasagna via coreboot wrote:
>> I really want to show my fan for you so if you have some stickers
>> for my laptop so I could brag it :) that will d
Vegetable Lasagna via coreboot wrote:
> I really want to show my fan for you so if you have some stickers
> for my laptop so I could brag it :) that will do my day.
When the coreboot.org wiki was online it was possible to download the
logo files and see the logo license terms.
That way, you could
Dear Peter, dear Michal,
Am 16.10.20 um 15:22 schrieb Michal Zygowski:
..
PCI: 00:15.0 init
PCI: 00:15.0 init finished in 0 msecs
PCI: 00:15.1 init
PCI: 00:15.1 init finished in 0 msecs
PCI: 00:18.1 init
PCI: 00:18.1 init finished in 0 msecs
Note that there is no init for 15.2 above. I don't
Christian Walter wrote:
> if we are sure it is behind 15.2 - one can also try to make it hidden.
Sounds like that's worth a try. How to do that?
//Peter
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Hi Peter,
> ..
>> PCI: 00:15.0 init
>> PCI: 00:15.0 init finished in 0 msecs
>> PCI: 00:15.1 init
>> PCI: 00:15.1 init finished in 0 msecs
>> PCI: 00:18.1 init
>> PCI: 00:18.1 init finished in 0 msecs
> Note that there is no init for 15.2 above. I don't know why, if it's
> enabled in the mainboard
Hi,
if we are sure it is behind 15.2 - one can also try to make it hidden.
This way the device will be enabled no matter what. If that solves the
problem - you need to investigate why coreboot does not enable the device.
Best,
Chris
On 10/16/20 3:05 PM, Peter Stuge wrote:
> Paul Menzel wrote:
>
Balaji Sivakumar wrote:
> Am working on adding a feature to upgrading the BIOS (complete
> IFD+ME+Coreboot) using intel-spi driver at the OS level. Able to
> successfully take the backup full 16MB spi nor flash data which
> includes IFD+ME+BIOS using flashrom Internal Programmer option and
> it is
Hi,
Please find the latest report on new defect(s) introduced to coreboot found
with Coverity Scan.
58 new defect(s) introduced to coreboot found with Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 20 of 58 defect(s)
** CID 1433626: Insecure data handling (TAINTED_SCALAR)
Paul Menzel wrote:
> With the vendor firmware 6601, it is
>
> 04:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd.
> RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168]
> (rev 09)
>
> behind PCI bridge 00:15.2.
..
> In the current state [1], coreboot says d
Hi Paul,
On 15.10.2020 10:53, Paul Menzel wrote:
Dear coreboot folks,
To get PCI bridge 0:15.2 enabled for the network device on the Asus
F2A85-M PRO, I want to debug the PCIe General Purpose Ports lane
configuration of the FCH.
I’d like to print some variables in
src/vendorcode/amd/a
Hi Paul,
I think I got it... It is pretty easy to enable the serial output. Just
define IDSOPT_TRACING_ENABLED to TRUE in
src/mainbaord/MAINBAORDDIR/OptionsIds.h . It will link the coreboot's
printk (debug level 7) to AGESA console. So if you enable serial port in
coreboot's Kconfig it will work o
Hi Paul,
See inline repsonses.
On 15.10.2020 20:04, Angel Pons wrote:
>
>> Clay
>>
>>
>> On Thu, Oct 15, 2020 at 3:54 AM Paul Menzel wrote:
>>> Dear coreboot folks,
>>>
>>>
>>> To get PCI bridge 0:15.2 enabled for the network device on the Asus
>>> F2A85-M PRO, I want to debug the PCIe General P
The documentation says
The main SPI flash can be accessed using flashrom, if the AmdSpiRomProtect
modules have been deleted in the factory image previously.
So what does that mean? How can i do that? I would like to flash it internal
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