[coreboot] New Defects reported by Coverity Scan for coreboot

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 2 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 1518657:(OVERRUN) __

[coreboot] Re: [RFC] Pre-Memory Sign-of-Life using Intel uGOP

Hi Jeremy, On 14.08.23 22:52, Compostella, Jeremy wrote: > We propose to take advantage of a proprietary driver Intel already supports, > validates and includes in FSP silicon: the Intel Graphics PEIM (Pre-EFI > Initialization Module) driver also known as the GOP (Graphical Output > Protocol) d

[coreboot] [coreboot - Bug #505] Intel Harcuvar CRB Denverton_NS С3000. Only 15 cores of a 16 core processor is defined in the operating system.

Issue #505 has been updated by Dmitry Ponamorev. Due date set to 08/22/2023 Assignee changed from Angel Pons to Dmitry Ponamorev % Done changed from 0 to 100 Estimated time set to 1.00 h Dmitry Ponamorev wrote: > Found a bug with the definition of not all processor cores of the Intel(R)

[coreboot] Re: linux boot failure on 440bx/i82371eb [asus/p2b & p2-99] after [acpi/acpi.c: Reduce boilerplate] change

Hi The mentioned board asus/p2b falls into a rare category of mainboards from around 1999 (?) when discrete southbridge silicon did not implement an IOAPIC. There is a hint in sb/intel/i82371eb/isa.c about enabling IOAPIC as a discrete component for SMP configurations. One thing I notice is that

[coreboot] [coreboot - Bug #505] (New) Intel Harcuvar CRB Denverton_NS С3000. Only 15 cores of a 16 core processor is defined in the operating system.

Issue #505 has been reported by Dmitry Ponamorev. Bug #505: Intel Harcuvar CRB Denverton_NS С3000. Only 15 cores of a 16 core processor is defined in the operating system. https://ticket.coreboot.org/issues/505 * Author: Dmitry Ponamorev * Status: