[coreboot] Re: Open letter to Intel regarding the PSE on Elkhart Lake

Yes, nice job Werner! Since you’ve been working on Elkhart Lake, can I inquire if you have booted it to an OS via eMMC and/or iPXE using coreboot? If so, with which payload? Thanks, - Jay From: ron minnich Sent: Friday, April 22, 2022 7:02 PM To: Zeh, Werner Cc: coreboot

[coreboot] Re: Git reports an interesting error message

Ok, I'm running into the same issue on an Ubuntu 16.04 system. $ git clone https://review.coreboot.org/coreboot.git Cloning into 'coreboot'... fatal: unable to access 'https://review.coreboot.org/coreboot.git/': server certificate verification failed. CAfile: /etc/ssl/certs/ca-certificates.crt

[coreboot] Re: A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).

Unfortunately, for the Denverton SoC (C3000 series), the APIC ID of the first core is not always the same. For 16-core SKUs, it’s always 0, but for SKUs with a lower number of cores, it may be a different number. It’s also possible (but not confirmed) that for a particular SKU (other than

[coreboot] Re: [RFC] Proposal to move all FSP 1.x binaries to "legacy" branch

would break the builds from this branch. Thanks, - Jay Jay Talbott Principal Consulting Engineer SysPro Consulting, LLC 3057 E. Muirfield St. Gilbert, AZ 85298 (480) 704-8045 (480) 445-9895 (FAX) jaytalb...@sysproconsulting.com http://www.sysproconsulting.com > -Original Message- >

[coreboot] Re: PCIe hotplug support with Intel FSP 2.0

device is detected. So the whole purpose of the PCIe hot plug settings in the FSP are simply to keep the root port from being automatically disabled if no device is connected to it at boot time. That’s all it does. - Jay Jay Talbott Principal Consulting Engineer SysPro Consulting, LLC 3057 E

[coreboot] Re: Regarding Intel CPU frequency (Intel Denverton based)

discovered in the original implementation. Without actually looking at the code, I believe both of these can be fixed in src/soc/intel/denverton_ns/cpu.c. - Jay Jay Talbott Principal Consulting Engineer SysPro Consulting, LLC 3057 E. Muirfield St. Gilbert, AZ 85298 (480) 704-8045 (480) 445-9895

[coreboot] Re: Removal of mainboard Intel/Strago

, I’ll see if I can get someone at Intel to look at it. I agree that it is problematic when what’s on the public FSP GitHub isn’t the latest version of the FSP and headers and such that people are actually using. This should defiantly be corrected. - Jay Jay Talbott Principal Consulting

[coreboot] Re: Intel Xeon D-1577 (16-core)

things and don't have the bandwidth to look into it deeper, but at least we have a pretty good idea of where the problem lies. - Jay Jay Talbott Principal Consulting Engineer SysPro Consulting, LLC 3057 E. Muirfield St. Gilbert, AZ 85298 (480) 704-8045 (480) 445-9895 (FAX) jaytalb

[coreboot] Re: Intel Xeon D-1577 (16-core)

point somebody needs to dig into the actual code in smmrelocate.c and identify the root cause of the actual race condition. We just haven't had the time to do any further investigation into the root cause since we have a working workaround. Hope that helps... - Jay Jay Talbott Principal Consulting

Re: [coreboot] Maintainer for FSP broadwell DE

Correction. I mean it successfully built and booted coreboot + a BuildRoot linux kernel payload (not SeaBIOS) on the Camelback Mountain CRB. - Jay Jay Talbott Principal Consulting Engineer SysPro Consulting, LLC 3057 E. Muirfield St. Gilbert, AZ 85298 (480) 704-8045 (480) 445-9895 (FAX) jaytalb

Re: [coreboot] Maintainer for FSP broadwell DE

We successfully built and booted coreboot + SeaBIOS on the Camelback Mountain CRB yesterday based on the head of the coreboot master branch. - Jay Jay Talbott Principal Consulting Engineer SysPro Consulting, LLC 3057 E. Muirfield St. Gilbert, AZ 85298 (480) 704-8045 (480) 445-9895 (FAX) jaytalb

Re: [coreboot] Maintainer for FSP broadwell DE

Jay Talbott Principal Consulting Engineer SysPro Consulting, LLC 3057 E. Muirfield St. Gilbert, AZ 85298 (480) 704-8045 (480) 445-9895 (FAX) jaytalb...@sysproconsulting.com http://www.sysproconsulting.com > -Original Message- > From: coreboot [mailto:coreboot-boun...@corebo

Re: [coreboot] Further coreboot releases, setting new standards

> From: Patrick Georgi [mailto:pgeo...@google.com] > Sent: Thursday, November 29, 2018 4:23 AM > To: mikeb...@gmail.com > Cc: Nico Huber; jaytalb...@sysproconsulting.com; coreboot > Subject: Re: [coreboot] Further coreboot releases, setting new standards > > Am Do., 29. Nov. 2018 um 11:59 Uhr

Re: [coreboot] Further coreboot releases, setting new standards

> -Original Message- > From: Arthur Heymans [mailto:art...@aheymans.xyz] > Sent: Wednesday, November 28, 2018 6:26 AM > To: Jay Talbott > Cc: Patrick Georgi via coreboot; Patrick Georgi > Subject: Re: [coreboot] Further coreboot releases, setting new standards > &g

Re: [coreboot] Further coreboot releases, setting new standards

Hi Paul, > -Original Message- > From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Paul > Menzel > Sent: Sunday, November 25, 2018 7:29 AM > To: Jay Talbott; Arthur Heymans; Patrick Georgi > Cc: coreboot@coreboot.org > Subject: Re: [coreboot] Furt

Re: [coreboot] Further coreboot releases, setting new standards

I know I don't post much here, but I feel like I need to chime in on this thread... Perhaps it's time that SysPro becomes a louder voice in the community.Bay Trail and Broadwell DE are both still very popular platforms, yet neither one of them meets the cut for any of the three criteria. So I

Re: [coreboot] Broadwell-DE hang in coreboot: mp_init.c

to this problem, or an understanding of why it only impacts Broadwell-DE, and yet isn't a problem on the Intel Camelback Mountain reference board? Since it's not reproducible on the Intel reference board, we can't get much support out of Intel on this one... Thanks, - Jay Jay Talbott Principal

[coreboot] Assigning PCI resources clobbers console with io-mapped / memory-mapped UART

other bad things to happen. I thought it best to bring this up to the coreboot community, since this could easily be a problem on any/all platforms that don't have a legacy UART (or a UART that can be put into legacy mode). Has anybody else run into this and/or thought about a general solution t

Re: [coreboot] Out of MTRRs

have in the system. Thanks, - Jay Jay Talbott Principal Consulting Engineer SysPro Consulting, LLC 3057 E. Muirfield St. Gilbert, AZ 85298 (480) 704-8045 (480) 445-9895 (FAX) jaytalb...@sysproconsulting.com http://www.sysproconsulting.com > -Original Message- > From: A

[coreboot] Out of MTRRs

on systems with larger amounts of RAM, so I figured I'd ask the community what's the fix to getting this to work correctly with 16GB of RAM before trying to figure it out myself. Any help would be most appreciated. Thanks, - Jay Jay Talbott Principal Consulting Engineer SysPro

Re: [coreboot] Has anyone built the memtest86+ payload recently?

it as an elf and use it as the primary payload for some validation checks on the memory – the normal/production payload is a Linux kernel. Thanks, - Jay From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Martin Roth Sent: Monday, March 12, 2018 10:18 AM To: Jay Talbott Cc

[coreboot] Has anyone built the memtest86+ payload recently?

One of my colleagues is trying to build the memtest86+ payload, and is running into build problems. Build environment is Ubuntu 16.0.4 LTS. Has anybody else run into this? Any guidance on how to resolve it? I'm hoping it's just something simple that needs to be changed in the build

[coreboot] Does the coreboot build system support external patches?

you can keep your changes is a directory tree separate from the FOSS tree. Then during the build step your patches get applied and compiled using another separate build tree. Thanks, - Jay Jay Talbott Principal Consulting Engineer SysPro Consulting, LLC 3057 E. Muirfield St. Gilbert, AZ

Re: [coreboot] Can coreboot for KabyLake rvp11 work on Intel Sasby Island kit?

. At least now I can finally start focusing on porting from the RVP7/RVP15 coreboot implementation to my client's board design... - Jay Jay Talbott Principal Consulting Engineer SysPro Consulting, LLC 3057 E. Muirfield St. Gilbert, AZ 85298 (480) 704-8045 (480) 445-9895 (FAX) jaytalb

Re: [coreboot] Can coreboot for KabyLake rvp11 work on Intel Sasby Island kit?

e FSP was initially developed to target Chromebooks. That being said, there's really no technical reason why one couldn't be use for the other application, and vice versa, except that support becomes a bit of a nightmare... - Jay Jay Talbott Principal Consulting Engineer SysPro Consulting, LLC

Re: [coreboot] Can coreboot for KabyLake rvp11 work on Intel Sasby Island kit?

a working solution just this week. I have no idea if/when the latest version of the FSP that I am now using which actually works on the RVP7 and RVP15 will be publicly released. That’s completely up to Intel. Just speaking from personal experience… - Jay Jay Talbott Principal

Re: [coreboot] Who has experience with the Intel RVP7 (or RVP15) CRB?

> I'm not sure what IFWI refers to. I thought it's only about the host > firmware (i.e. the BIOS region of the flash). Make sure the other > regions are restored as well. If you have an image of the factory > firmware (not a backup), I'd try to flash that. > IFWI - Integrated Firmware Image

Re: [coreboot] Who has experience with the Intel RVP7 (or RVP15) CRB?

things to where they were before introducing coreboot, but not in this case... I'm dead in the water if the CRB is bricked... - Jay Jay Talbott Principal Consulting Engineer SysPro Consulting, LLC 3057 E. Muirfield St. Gilbert, AZ 85298 (480) 704-8045 (480) 445-9895 (FAX) jaytalb...@sysproconsulting.co

Re: [coreboot] Who has experience with the Intel RVP7 (or RVP15) CRB?

, as if it’s otherwise dead. Furthermore, restoring the factory UEFI BIOS no longer boots either. Now what? Any suggestions? - Jay Jay Talbott Principal Consulting Engineer SysPro Consulting, LLC 3057 E. Muirfield St. Gilbert, AZ 85298 (480) 704-8045 (480) 445-9895 (FAX) jaytalb

Re: [coreboot] Who has experience with the Intel RVP7 (or RVP15) CRB?

Hi Matt, I’ll try XIP and see what happens… but how would that impact the UPD signature? The signature is defined in coreboot/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h, as well as in FspUpd.h in the headers included with the FSP on GitHub. - Jay Jay Talbott Principal

Re: [coreboot] Who has experience with the Intel RVP7 (or RVP15) CRB?

us folks, including the individual that upstreamed the RVP7 support to coreboot and the individual who published the FSP to GitHub, which remain unanswered. Any help from the coreboot community would be most appreciated! Thanks! - Jay Jay Talbott Principal Consulting Engineer SysPro Consulting, LL

[coreboot] Who has experience with the Intel RVP7 (or RVP15) CRB?

rmore, I have yet to get the serial console working on the DB-9 serial port. I have the jumpers on the board configured to connect it to UART #2, and configured in coreboot accordingly, but I get nothing for console output. Any help would be most appreciated! Thanks, - Jay Jay Talb

Re: [coreboot] Regarding offset adjustment for building coreboot.

The FSP is rebased with the Intel BCT tool, not the FITC tool. > On Apr 8, 2016, at 7:38 AM, Martin Roth wrote: > > Not knowing which platform this is makes it a little harder to > determine what's locked in place. We'd also need to know if this is > getting built from the