ping3?
On Mon, Jan 31, 2011 at 12:53 PM, Keith Hui buu...@gmail.com wrote:
On Fri, Jan 14, 2011 at 3:47 AM, Roger rogerx@gmail.com wrote:
On Tue, Jan 11, 2011 at 11:17:17PM -0500, Keith Hui wrote:
Hi all,
Here is the new L2 cache patch. Sign-off in the patch itself. Still
very juicy and
On Tue, Jan 11, 2011 at 11:17:17PM -0500, Keith Hui wrote:
Hi all,
Here is the new L2 cache patch. Sign-off in the patch itself. Still
very juicy and tasty at 25k. :D
Also done is including cpu/intel/model_68x again in slot_1. Otherwise
it will die with a Coppermine P3 installed.
My boot log on
On Tue, Jan 11, 2011 at 11:17:17PM -0500, Keith Hui wrote:
Hi all,
Here is the new L2 cache patch. Sign-off in the patch itself. Still
very juicy and tasty at 25k. :D
Also done is including cpu/intel/model_68x again in slot_1. Otherwise
it will die with a Coppermine P3 installed.
My boot log on
...@gmail.com, Idwer Vollering
vid...@gmail.com, Roger rogerx@gmail.com
Subject: Re: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love
this
Date: Tue, 11 Jan 2011 23:17:17 -0500
Hi all,
Here is the new L2 cache patch. Sign-off in the patch itself. Still
very juicy and tasty at 25k. :D
jtmett...@gmail.com, Idwer Vollering vid...@gmail.com,
Roger rogerx@gmail.com
Subject: Re: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this
Date: Tue, 11 Jan 2011 23:17:17 -0500
Hi all,
Here is the new L2 cache patch. Sign-off in the patch itself. Still
very juicy and tasty
On Wed, Jan 12, 2011 at 10:55:37PM -0500, Keith Hui wrote:
The L2 cache on a Coppermine doesn't need any special enabling
sequence. I just put a 1GHz Coppermine into my board and it boots fine
showing the full 256k cache. This patch doesn't even apply to them
anyway.
FYI: Have 450P3 and 2x750P3's
On Tue, Jan 11, 2011 at 11:17:17PM -0500, Keith Hui wrote:
Hi all,
Here is the new L2 cache patch. Sign-off in the patch itself. Still
very juicy and tasty at 25k. :D
Also done is including cpu/intel/model_68x again in slot_1. Otherwise
it will die with a Coppermine P3 installed.
ug. I'm
I've applied the patch here and have been testing on a Tyan 1832DL using the
Tyan 1846 mainboard and am not seeing any of the patch's printk output within
the logs here.
I have grepped for L2 rdmsr.
I can see where one of the patch files links in SLOT1 cpu with
the 67x cpu. Can also see where
Here is updated patch with l2_cache.c added.
Signed-off-by: Jouni Mettälä jtmett...@gmail.com
Index: src/cpu/intel/model_67x/l2_cache.c
===
--- src/cpu/intel/model_67x/l2_cache.c (revision 0)
+++ src/cpu/intel/model_67x/l2_cache.c
On Sat, Jan 08, 2011 at 12:25:36PM +, Jouni Mettälä wrote:
Here is updated patch with l2_cache.c added.
Signed-off-by: Jouni Mettälä [1]jtmett...@gmail.com
CC mainboard/tyan/s1846/crt0.s
CC mainboard/tyan/s1846/crt0.romstage.o
make: *** No rule to make target
On Sat, Jan 8, 2011 at 5:25 AM, Jouni Mettälä jtmett...@gmail.com wrote:
Here is updated patch with l2_cache.c added.
I think it's missing l2_cache.h now.
Thanks,
Myles
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coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Updated patch with l2_cache.h added
Signed-off-by: Jouni Mettälä jtmett...@gmail.com
Index: src/include/cpu/intel/l2_cache.h
===
--- src/include/cpu/intel/l2_cache.h (revision 0)
+++ src/include/cpu/intel/l2_cache.h (revision 0)
@@
On Sat, Jan 08, 2011 at 08:37:53PM +, Jouni Mettälä wrote:
Updated patch with l2_cache.h added
Signed-off-by: Jouni Mettälä [1]jtmett...@gmail.com
References
Visible links
1. mailto:jtmett...@gmail.com
OK. V3 compiled file. My previous uart missing file looks to be my fault for
Hi
Parts of original patch are already in coreboot. This version made cache
work in my board now. It might need work so it doesn't break others. Here is
part of serial capture. Rest is attached
Initializing CPU #0
CPU: vendor Intel device 673
CPU: family 06, model 07, stepping 03
microcode_info:
On Fri, Jan 07, 2011 at 10:45:40PM +0200, Jouni Mettälä wrote:
Hi
Parts of original patch are already in coreboot. This version made cache
work in my board now. It might need work so it doesn't break others. Here
is part of serial capture. Rest is attached
Got the following on
2011/1/8 Roger rogerx@gmail.com
On Fri, Jan 07, 2011 at 10:45:40PM +0200, Jouni Mettälä wrote:
Hi
Parts of original patch are already in coreboot. This version made
cache
work in my board now. It might need work so it doesn't break others.
Here
is part of serial capture.
On Sat, Jan 08, 2011 at 03:22:15AM +0100, Idwer Vollering wrote:
2011/1/8 Roger [1]rogerx@gmail.com
On Fri, Jan 07, 2011 at 10:45:40PM +0200, Jouni Mettälä wrote:
Hi
Parts of original patch are already in coreboot. This version made
cache
work in my board
ping... Is this too much? :-)
On Thu, May 13, 2010 at 10:03 PM, Keith Hui buu...@gmail.com wrote:
Hi all,
This is it. The 72oz steak. ;-) It is ~180k seasoned with a few other
related changes (below), so it is gzipped. I may have committed a few
crimes here, but anyway...
This patch:
1.
ping... Is this too much? :-)
Please don't gzip patches, it lowers the chance of someone reviewing
them to zero ;-)
There is 65x microcode in the model_67x directory, and it's not split up
into single files as for the other CPUs.
+ if (cpuid_res.ebx != 0x756e6547 || cpuid_res.edx !=
2010/5/14 Keith Hui buu...@gmail.com
The original patch was unclean as pork (didn't apply cleanly). Please
use this one instead.
Thanks Joseph.
And edit your board's romstage similar to patch below:
Index: src/mainboard/asus/p2b-ls/romstage.c
2010/5/14 Keith Hui buu...@gmail.com
BTW enable CAR and try again.
Like this (note that it doesn't boot my asus p2b, rev 1.04):
svn diff src/mainboard/asus/p2b/Kconfig
Index: src/mainboard/asus/p2b/Kconfig
===
---
Limit your DCACHE_RAM_SIZE to 0x1000 (4k). The L2 init is done
post-raminit so it's not available for CAR. Your CPU only has 16k of
L1 cache available for CAR.
HTH
Keith
On Fri, May 14, 2010 at 12:51 PM, Idwer Vollering vid...@gmail.com wrote:
2010/5/14 Keith Hui buu...@gmail.com
BTW enable
Forgive my ignorance, but are there super-compact boards that use this
hardware?
some kind of low-cost low power thing? Or are there just old systems :-)
thanks
ron
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coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Mine is an old system, I'm going to use it for serial debugging my desktop
machine when I put coreboot there.
On May 14, 2010 3:07 PM, ron minnich rminn...@gmail.com wrote:
Forgive my ignorance, but are there super-compact boards that use this
hardware?
some kind of low-cost low power thing?
On 05/13/2010 10:03 PM, Keith Hui wrote:
Hi all,
This is it. The 72oz steak. ;-) It is ~180k seasoned with a few other
related changes (below), so it is gzipped. I may have committed a few
crimes here, but anyway...
First, I found out why the debug output isn't correct - A typo caused
the
On Thu, May 13, 2010 at 10:28 PM, Joseph Smith j...@settoplinux.org wrote:
On 05/13/2010 10:03 PM, Keith Hui wrote:
Hi all,
This is it. The 72oz steak. ;-) It is ~180k seasoned with a few other
related changes (below), so it is gzipped. I may have committed a few
crimes here, but anyway...
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