Hi In the code for intel model_6ex there is a comment "TODO Do we want Deep C4 and Dynamic L2 shrinking".
On later targets (6fx and 1067) this is done setting some bits in IA32_MISC_ENABLE and MSR_PMG_CST_CONFIG_CONTROL msr. It tried setting the same bits, which should upgrade C2 to C2E and C4 to C4E. The results is that the C2 state consumes noticeably less power. (C4 remains similar in power consumption) Those msr bits are mentioned in intel datasheets on those cpus: http://download.intel.com/design/mobile/datashts/30922106.pdf I can't find documentation on those bits. In the "Intel® 64 and IA-32 Architectures Software Developer’s Manual" those bits are marked as reserved... I would like to know more about this, so if someone can help me on this... -- Arthur Heymans -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
