Hello,
I would like to report that I asserted GPIO23 early in the boot
process from auto.c and my ethernet is now powering on:-)
coreboot detects it and sets it up:-)
Although I don't think it is setup all the way though, I can't get it
to obtain a ip address in Linux from DHCP. I may have to
Sweet:-)
With Stefan's great tool I think I found my ethernet enable GPIO!!
I run it with the original bios (ethernet enabled) and then with the
original bios (ethernet disabled). The only difference is in the 0x0C
register looks like GPIO 23 is drivin to high (asserted), enabling the
LAN
On Tue, 19 Feb 2008, [EMAIL PROTECTED] wrote:
Quoting Peter Stuge [EMAIL PROTECTED]:
[..]
dd if=/dev/ioport bs=1 skip=$[0xbasehere] count=asmanyasyouwant | xxd
3. What is the pipe xxd for?
The default output of dd is stdout, so it writes stdout to file xxd.
However, why not use of=xxd
Sorry for joining in late. I wrote a utility a while ago that dumped the
GPIO registers of an ICH7. Maybe your registers look pretty similar.
My output is something like:
Intel Southbridge: 8086:27b8
GPIOBASE = 0x0480
gpiobase+0x: 0x1f1ff7c0
gpiobase+0x0004: 0xe0e8efc3
gpiobase+0x0008:
Quoting Stefan Reinauer [EMAIL PROTECTED]:
Sorry for joining in late. I wrote a utility a while ago that dumped the
GPIO registers of an ICH7. Maybe your registers look pretty similar.
My output is something like:
Intel Southbridge: 8086:27b8
GPIOBASE = 0x0480
gpiobase+0x: 0x1f1ff7c0
Russell Whitaker skrev:
On Tue, 19 Feb 2008, [EMAIL PROTECTED] wrote:
Quoting Peter Stuge [EMAIL PROTECTED]:
[..]
dd if=/dev/ioport bs=1 skip=$[0xbasehere] count=asmanyasyouwant | xxd
3. What is the pipe xxd for?
The default output of dd is stdout, so it
Hi all,
Just a note. Isadump util form Lm-sensors can do the SIO dumps as well
as flat io dumps. It can even unlock the SIO with a key :)
Supports SIO LDNs etc etc.
Rudolf
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Quoting Tom Sylla [EMAIL PROTECTED]:
The dump tool is the way to go now, but just to answer a couple of your
questions:
[EMAIL PROTECTED] wrote:
OK, so lets clarify?
GPIOBASE?GPIO Base Address (LPC I/F?D31:F0)
31:16 Reserved
15:6 Base Address ? R/W. Provides the 64 bytes of I/O space for
The dump tool is the way to go now, but just to answer a couple of your
questions:
[EMAIL PROTECTED] wrote:
OK, so lets clarify?
GPIOBASE?GPIO Base Address (LPC I/F?D31:F0)
31:16 Reserved
15:6 Base Address ? R/W. Provides the 64 bytes of I/O space for GPIO.
5:1 Reserved
0 Resource
* [EMAIL PROTECTED] [EMAIL PROTECTED] [080219 15:40]:
I wish you would have brought this up earlier
Sorry. I had it on my CF disk for a while :(
As Ron said btw, this type of tool is incredibly useful, as you doubtless
know. I think we should mofify it for all the ICH's and add it to
Quoting Stefan Reinauer [EMAIL PROTECTED]:
* [EMAIL PROTECTED] [EMAIL PROTECTED] [080219 15:40]:
I wish you would have brought this up earlier
Sorry. I had it on my CF disk for a while :(
As Ron said btw, this type of tool is incredibly useful, as you doubtless
know. I think we should
On 18.02.2008 02:45, [EMAIL PROTECTED] wrote:
Quoting Carl-Daniel Hailfinger [EMAIL PROTECTED]:
On 16.02.2008 17:57, [EMAIL PROTECTED] wrote:
Hello,
How do I dump the GPIO I/O Registers in linux. I need to dump the
GPIO's from the southbridge. Anyone?
Depends on the
Quoting Carl-Daniel Hailfinger [EMAIL PROTECTED]:
On 18.02.2008 03:25, Peter Stuge wrote:
On Sun, Feb 17, 2008 at 09:15:55PM -0500, [EMAIL PROTECTED] wrote:
It can't be probed easily, but perhaps reverse engineered with a
bit of effort.
You mean just probing the GPIO pins with a meter to
If you want to look at the GPIOs, from the 82801DB datasheet, it looks
like you should look at:
9.1.14 GPIOBASE—GPIO Base Address (LPC I/F—D31:F0)
and
9.1.15 GPIO_CNTL—GPIO Control (LPC I/F—D31:F0)
(offsets 58 and 5c in D31:f0, lspci -xxx as root is one way to dump)
What value is in those
I think you guys are going in circles :-)
Here is my chance to help :-)
For the last gazillion years the IO ports on the intel parts have been
about the same. You could probably even reference an old PIIX document
to see how they are programmed. (you'd be surprised how much all the
new stuff
Quoting ron minnich [EMAIL PROTECTED]:
I think you guys are going in circles :-)
Here is my chance to help :-)
For the last gazillion years the IO ports on the intel parts have been
about the same. You could probably even reference an old PIIX document
to see how they are programmed.
On Mon, Feb 18, 2008 at 07:45:55PM -0500, [EMAIL PROTECTED] wrote:
Once you have the base address, you can read the GPIO control
registers from /dev/port, with the seek equal to the base address.
How?? This is the part I am looking for, this would be the golden
ticket:-)
Oh! This can be
?
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
On
Behalf Of [EMAIL PROTECTED]
Sent: Saturday, February 16, 2008 11:58 AM
To: Coreboot
Subject: [coreboot] Dump GPIO I/O Registers
Hello,
How do I dump the GPIO I/O Registers in linux. I need to dump the
GPIO's from
On Sun, Feb 17, 2008 at 08:38:30PM -0500, [EMAIL PROTECTED] wrote:
I need something that will probe the GPIO's to find out which one is
asserted and if the signal is in or out? Does that make more sense?
Unfortunately you are now at the point where you would need the board
schematic.
It can't
Quoting Carl-Daniel Hailfinger [EMAIL PROTECTED]:
On 16.02.2008 17:57, [EMAIL PROTECTED] wrote:
Hello,
How do I dump the GPIO I/O Registers in linux. I need to dump the
GPIO's from the southbridge. Anyone?
Depends on the southbridge. It could be directly/indirectly
memory-mapped or
Hello,
How do I dump the GPIO I/O Registers in linux. I need to dump the
GPIO's from the southbridge. Anyone?
Thanks - Joe
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will be with you always. Obi-Wan Kenobi
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
On
Behalf Of [EMAIL PROTECTED]
Sent: Saturday, February 16, 2008 11:58 AM
To: Coreboot
Subject: [coreboot] Dump GPIO I/O Registers
Hello,
How do I dump the GPIO I/O Registers
On 16.02.2008 17:57, [EMAIL PROTECTED] wrote:
Hello,
How do I dump the GPIO I/O Registers in linux. I need to dump the
GPIO's from the southbridge. Anyone?
Depends on the southbridge. It could be directly/indirectly
memory-mapped or port-based. Simply tell us what the data sheet says
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