Kyösti Mälkki (kyosti.mal...@gmail.com) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/324
-gerrit
commit ee4e02a4bc9e25d4c6eb6fb1f2ed8d3d825393a1
Author: Kyösti Mälkki <kyosti.mal...@gmail.com>
Date: Sat Oct 22 20:37:29 2011 +0300
Conditionally use CACHE_AS_RAM
Handle cases where CPU has CACHE_AS_RAM, but mainboard has not
been converted.
Change-Id: Ia4c24333fa4175488b1eb007c9582d21140c69e7
Signed-off-by: Kyösti Mälkki <kyosti.mal...@gmail.com>
---
src/arch/x86/Kconfig | 7 +++++++
src/console/Makefile.inc | 2 +-
src/cpu/amd/model_gx2/syspreinit.c | 2 +-
src/cpu/amd/model_lx/syspreinit.c | 2 +-
src/cpu/x86/mtrr/earlymtrr.c | 2 +-
src/include/assert.h | 2 +-
src/include/cpu/x86/bist.h | 2 +-
src/lib/Makefile.inc | 2 +-
src/lib/generic_sdram.c | 2 +-
src/lib/ramtest.c | 24 ++++++++++++------------
src/northbridge/intel/e7501/debug.c | 32 ++++++++++++++++----------------
src/northbridge/intel/i3100/raminit.c | 2 +-
12 files changed, 44 insertions(+), 37 deletions(-)
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 7575759..d512eb9 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -44,6 +44,13 @@ config TINY_BOOTBLOCK
default n if MAYBE_TINY_BOOTBLOCK
default y
+# Really a synonym for TINY_BOOTBLOCK now
+config USE_CACHE_AS_RAM
+ bool
+ default n if NO_TINY_BOOTBLOCK
+ default n if MAYBE_TINY_BOOTBLOCK
+ default y
+
config BIG_BOOTBLOCK
bool
default n if TINY_BOOTBLOCK
diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc
index 4a30918..ae0e997 100644
--- a/src/console/Makefile.inc
+++ b/src/console/Makefile.inc
@@ -9,7 +9,7 @@ smm-y += printk.c
smm-y += vtxprintf.c
romstage-y += vtxprintf.c
-romstage-$(CONFIG_CACHE_AS_RAM) += console.c
+romstage-$(CONFIG_USE_CACHE_AS_RAM) += console.c
romstage-y += post.c
romstage-y += die.c
diff --git a/src/cpu/amd/model_gx2/syspreinit.c
b/src/cpu/amd/model_gx2/syspreinit.c
index 8140348..4a6a837 100644
--- a/src/cpu/amd/model_gx2/syspreinit.c
+++ b/src/cpu/amd/model_gx2/syspreinit.c
@@ -13,7 +13,7 @@ static void StartTimer1(void)
void SystemPreInit(void)
{
/* they want a jump ... */
-#if !CONFIG_CACHE_AS_RAM
+#if !CONFIG_USE_CACHE_AS_RAM
__asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");
#endif
StartTimer1();
diff --git a/src/cpu/amd/model_lx/syspreinit.c
b/src/cpu/amd/model_lx/syspreinit.c
index 35c54fb..fcedfe2 100644
--- a/src/cpu/amd/model_lx/syspreinit.c
+++ b/src/cpu/amd/model_lx/syspreinit.c
@@ -39,7 +39,7 @@ void SystemPreInit(void)
{
/* they want a jump ... */
-#if !CONFIG_CACHE_AS_RAM
+#if !CONFIG_USE_CACHE_AS_RAM
__asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");
#endif
StartTimer1();
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index dcfcccd..85cbfb5 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -20,7 +20,7 @@ static void set_var_mtrr(
wrmsr(MTRRphysMask_MSR(reg), maskm);
}
-#if !defined(CONFIG_CACHE_AS_RAM) || (CONFIG_CACHE_AS_RAM == 0)
+#if !defined(CONFIG_USE_CACHE_AS_RAM) || (CONFIG_USE_CACHE_AS_RAM == 0)
static void cache_lbmem(int type)
{
/* Enable caching for 0 - 1MB using variable mtrr */
diff --git a/src/include/assert.h b/src/include/assert.h
index 346e769..98cdfea 100644
--- a/src/include/assert.h
+++ b/src/include/assert.h
@@ -20,7 +20,7 @@
#ifndef __ASSERT_H__
#define __ASSERT_H__
-#if defined(__PRE_RAM__) && !CONFIG_CACHE_AS_RAM
+#if defined(__PRE_RAM__) && !CONFIG_USE_CACHE_AS_RAM
/* ROMCC versions */
#define ASSERT(x) { \
diff --git a/src/include/cpu/x86/bist.h b/src/include/cpu/x86/bist.h
index d1646bf..b4f2d2d 100644
--- a/src/include/cpu/x86/bist.h
+++ b/src/include/cpu/x86/bist.h
@@ -4,7 +4,7 @@
static void report_bist_failure(u32 bist)
{
if (bist != 0) {
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_EMERG, "BIST failed: %08x", bist);
#else
print_emerg("BIST failed: ");
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index b207ffe..667cf8f 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -6,7 +6,7 @@ romstage-y += memcmp.c
romstage-y += cbfs.c
romstage-y += lzma.c
#romstage-y += lzmadecode.c
-romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c
+romstage-$(CONFIG_USE_CACHE_AS_RAM) += ramtest.c
romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c
romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
diff --git a/src/lib/generic_sdram.c b/src/lib/generic_sdram.c
index efb61db..7e2ff8b 100644
--- a/src/lib/generic_sdram.c
+++ b/src/lib/generic_sdram.c
@@ -2,7 +2,7 @@
static inline void print_debug_sdram_8(const char *strval, uint32_t val)
{
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "%s%02x\n", strval, val);
#else
print_debug(strval); print_debug_hex8(val); print_debug("\n");
diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c
index 3f4657f..9323f76 100644
--- a/src/lib/ramtest.c
+++ b/src/lib/ramtest.c
@@ -53,7 +53,7 @@ static void ram_fill(unsigned long start, unsigned long stop)
/*
* Fill.
*/
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "DRAM fill: 0x%08lx-0x%08lx\n", start, stop);
#else
print_debug("DRAM fill: ");
@@ -65,7 +65,7 @@ static void ram_fill(unsigned long start, unsigned long stop)
for(addr = start; addr < stop ; addr += 4) {
/* Display address being filled */
if (!(addr & 0xfffff)) {
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "%08lx \r", addr);
#else
print_debug_hex32(addr);
@@ -75,7 +75,7 @@ static void ram_fill(unsigned long start, unsigned long stop)
write_phys(addr, (u32)addr);
};
/* Display final address */
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "%08lx\nDRAM filled\n", addr);
#else
print_debug_hex32(addr);
@@ -90,7 +90,7 @@ static void ram_verify(unsigned long start, unsigned long
stop)
/*
* Verify.
*/
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "DRAM verify: 0x%08lx-0x%08lx\n", start, stop);
#else
print_debug("DRAM verify: ");
@@ -103,7 +103,7 @@ static void ram_verify(unsigned long start, unsigned long
stop)
unsigned long value;
/* Display address being tested */
if (!(addr & 0xfffff)) {
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "%08lx \r", addr);
#else
print_debug_hex32(addr);
@@ -113,7 +113,7 @@ static void ram_verify(unsigned long start, unsigned long
stop)
value = read_phys(addr);
if (value != addr) {
/* Display address with error */
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_ERR, "Fail: @0x%08lx Read value=0x%08lx\n",
addr, value);
#else
print_err("Fail: @0x");
@@ -124,7 +124,7 @@ static void ram_verify(unsigned long start, unsigned long
stop)
#endif
i++;
if(i>256) {
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "Aborting.\n");
#else
print_debug("Aborting.\n");
@@ -134,14 +134,14 @@ static void ram_verify(unsigned long start, unsigned long
stop)
}
}
/* Display final address */
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "%08lx", addr);
#else
print_debug_hex32(addr);
#endif
if (i) {
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n");
#else
print_debug("\nDRAM did _NOT_ verify!\n");
@@ -149,7 +149,7 @@ static void ram_verify(unsigned long start, unsigned long
stop)
die("DRAM ERROR");
}
else {
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "\nDRAM range verified.\n");
#else
print_debug("\nDRAM range verified.\n");
@@ -165,7 +165,7 @@ void ram_check(unsigned long start, unsigned long stop)
* test than a "Is my DRAM faulty?" test. Not all bits
* are tested. -Tyson
*/
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "Testing DRAM : %08lx - %08lx\n", start, stop);
#else
print_debug("Testing DRAM : ");
@@ -178,7 +178,7 @@ void ram_check(unsigned long start, unsigned long stop)
/* Make sure we don't read before we wrote */
phys_memory_barrier();
ram_verify(start, stop);
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "Done.\n");
#else
print_debug("Done.\n");
diff --git a/src/northbridge/intel/e7501/debug.c
b/src/northbridge/intel/e7501/debug.c
index f19de0c..45c1edd 100644
--- a/src/northbridge/intel/e7501/debug.c
+++ b/src/northbridge/intel/e7501/debug.c
@@ -39,7 +39,7 @@ static void dump_pci_device(unsigned dev)
for(i = 0; i < 256; i++) {
unsigned char val;
if ((i & 0x0f) == 0) {
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "\n%02x:",i);
#else
print_debug("\n");
@@ -48,7 +48,7 @@ static void dump_pci_device(unsigned dev)
#endif
}
val = pci_read_config8(dev, i);
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, " %02x", val);
#else
print_debug_char(' ');
@@ -101,7 +101,7 @@ static inline void dump_spd_registers(const struct
mem_controller *ctrl)
device = ctrl->channel0[i];
if (device) {
int j;
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
#else
print_debug("dimm: ");
@@ -113,7 +113,7 @@ static inline void dump_spd_registers(const struct
mem_controller *ctrl)
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "\n%02x: ", j);
#else
print_debug("\n");
@@ -126,7 +126,7 @@ static inline void dump_spd_registers(const struct
mem_controller *ctrl)
break;
}
byte = status & 0xff;
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "%02x ", byte);
#else
print_debug_hex8(byte);
@@ -138,7 +138,7 @@ static inline void dump_spd_registers(const struct
mem_controller *ctrl)
device = ctrl->channel1[i];
if (device) {
int j;
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
#else
print_debug("dimm: ");
@@ -150,7 +150,7 @@ static inline void dump_spd_registers(const struct
mem_controller *ctrl)
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "\n%02x: ", j);
#else
print_debug("\n");
@@ -163,7 +163,7 @@ static inline void dump_spd_registers(const struct
mem_controller *ctrl)
break;
}
byte = status & 0xff;
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "%02x ", byte);
#else
print_debug_hex8(byte);
@@ -181,7 +181,7 @@ static inline void dump_smbus_registers(void)
for(device = 1; device < 0x80; device++) {
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "smbus: %02x", device);
#else
print_debug("smbus: ");
@@ -195,7 +195,7 @@ static inline void dump_smbus_registers(void)
break;
}
if ((j & 0xf) == 0) {
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "\n%02x: ",j);
#else
print_debug("\n");
@@ -204,7 +204,7 @@ static inline void dump_smbus_registers(void)
#endif
}
byte = status & 0xff;
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "%02x ", byte);
#else
print_debug_hex8(byte);
@@ -219,7 +219,7 @@ static inline void dump_io_resources(unsigned port)
{
int i;
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "%04x:\n", port);
#else
print_debug_hex16(port);
@@ -228,7 +228,7 @@ static inline void dump_io_resources(unsigned port)
for(i=0;i<256;i++) {
uint8_t val;
if ((i & 0x0f) == 0) {
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "%02x:", i);
#else
print_debug_hex8(i);
@@ -236,7 +236,7 @@ static inline void dump_io_resources(unsigned port)
#endif
}
val = inb(port);
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, " %02x",val);
#else
print_debug_char(' ');
@@ -255,7 +255,7 @@ static inline void dump_mem(unsigned start, unsigned end)
print_debug("dump_mem:");
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, "\n%08x:", i);
#else
print_debug("\n");
@@ -263,7 +263,7 @@ static inline void dump_mem(unsigned start, unsigned end)
print_debug(":");
#endif
}
-#if CONFIG_CACHE_AS_RAM
+#if CONFIG_USE_CACHE_AS_RAM
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char
*)i));
#else
print_debug(" ");
diff --git a/src/northbridge/intel/i3100/raminit.c
b/src/northbridge/intel/i3100/raminit.c
index ced3de1..a417336 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -1197,7 +1197,7 @@ static void sdram_enable(int controllers, const struct
mem_controller *ctrl)
pci_write_config16(ctrl->f0, MCHSCRB, data16);
/* The memory is now setup, use it */
-#if CONFIG_CACHE_AS_RAM == 0
+#if CONFIG_USE_CACHE_AS_RAM == 0
cache_lbmem(MTRR_TYPE_WRBACK);
#endif
}
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
