[coreboot] Re: Howdy!

2019-11-12 Thread Eli Duttman
I'm, perhaps, 1 micron closer to the objective. The 30 pin SIMM diagram (link follows immediately) tells the tale. https://allpinouts.org/pinouts/connectors/memory/dram-simm-30-pin/ It comes down to whether or not the chipset can drive the A11 line, at the appropriate times. A11 is connected

[coreboot] Re: Howdy!

2019-11-11 Thread Eli Duttman
x Held Sent: Monday, November 11, 2019 2:29 AM To: Eli Duttman Cc: coreboot@coreboot.org Subject: Re: [coreboot] Re: Howdy! Hi! > Since you mentioned that the system is using an EPROM, what type is it? Maybe > there's a way to emulate it If it's a parallel eeprom/nor flash, the memsim2 mig

[coreboot] Re: Howdy!

2019-11-10 Thread Felix Held
Hi! Since you mentioned that the system is using an EPROM, what type is it? Maybe there's a way to emulate it If it's a parallel eeprom/nor flash, the memsim2 might be worth a look. Beware though that if the mainboard has +12V connected to the programming voltage pin or another unused pin

[coreboot] Re: Howdy!

2019-11-08 Thread Eli Duttman
Thanksfor the pushes in the right direction. I'm probably in WAY over my head. Definitely not the LAs, ZAPs, CLCs ... that I'm familiar/comfortable with and that stuff has gone stale over the 2+ years, since retirement. In any event, I downloaded the Git archive. It turns out that page 90

[coreboot] Re: Howdy!

2019-11-08 Thread Patrick Georgi via coreboot
--- > *From:* Felix Held > *Sent:* Thursday, November 7, 2019 7:55 PM > *To:* coreboot@coreboot.org > *Subject:* [coreboot] Re: Howdy! > > > > > Using an old (pre romcc-romstage removal) coreboot version or even > linuxbios (not to

[coreboot] Re: Howdy!

2019-11-07 Thread Eli Duttman
. From: Felix Held Sent: Thursday, November 7, 2019 7:55 PM To: coreboot@coreboot.org Subject: [coreboot] Re: Howdy! > Using an old (pre romcc-romstage removal) coreboot version or even linuxbios (not to be confused with linuxboot) is probably your best

[coreboot] Re: Howdy!

2019-11-07 Thread Felix Held
Hi! You need either to use cache as RAM On those very old processors and chipsets it's rather unlikely that you'll get cache as RAM working, since those are typically missing some rather essential functionality for that; mostly that they don't have MTRRs. Using romcc would probably be an

[coreboot] Re: Howdy!

2019-11-07 Thread Eli Duttman
Rudolf, That you took time to respond to a NOOB, at all, is highly appreciated. It's definitely C 101 time for me. I'm an assembly language programmer and COBOL is number 2. I've previously looked into C but (now unfortunately) developed a distaste for it, given its claims of "universality"