On Fri, Feb 08, 2008 at 08:55:50AM -0500, [EMAIL PROTECTED] wrote:
1: set up csr memory/io base in the nic. ami bios uses 0xff7ff000
for mem base, and 0xdc01 as io base, these values should work to
test with.
I think your right Corey, we need to setup space for for the CSR
register
Quoting Peter Stuge [EMAIL PROTECTED]:
This is unfortunately at a later point in time. Anything to do with
CSR needs PCI config registers to be working properly. One hint is
BARs - Base Address Registers, which are stored in PCI config
registers.
Sorry I keep shooting down ideas. :\
Quoting Corey Osgood [EMAIL PROTECTED]:
I apologize if this seems disorganized, I'm trying to work it out:
1: set up csr memory/io base in the nic. ami bios uses 0xff7ff000 for mem
base, and 0xdc01 as io base, these values should work to test with.
Datasheet contradicts itself, says bits 3:0
On Feb 7, 2008 12:45 PM, Marc Karasek [EMAIL PROTECTED] wrote:
Let me add me two cents..
I have dealt with the Intel MACs in the past so let me dreg up some
memorries...
From what I recall, you had a serial eeprom on the board that
contained the init for the chip. This was the 82545GM.
Another missed cc.
On Feb 7, 2008 5:46 PM, Corey Osgood [EMAIL PROTECTED] wrote:
On Feb 7, 2008 5:02 PM, [EMAIL PROTECTED] wrote:
Quoting Marc Karasek [EMAIL PROTECTED]:
Let me add me two cents..
I have dealt with the Intel MACs in the past so let me dreg up some
memorries...
On Tue, Feb 05, 2008 at 10:51:39AM -0500, [EMAIL PROTECTED] wrote:
So I found this in the ICH4 datasheet:
The LAN controller enters Wake on LAN mode after reset if the Wake
on LAN bit in the EEPROM is set *(which it is)*.
You could try changing this bit in the EEPROM before running
coreboot
From the datasheet:
In the LAN controller the D0 state is partitioned into two substates, D0
Uninitialized (D0u) and D0 Active (D0a). [...] Initialization of the CSR,
Memory, or I/O Base Registers in the PCI Configuration space switches the
LAN controller D0u state to the D0a state.
and
The
Hello,
I would like to report that with ethtool under the original bios I am
able to dump the 82562ET eeprom registers:
0010 957a d175 1a03 0201 4701
49b2 8086 007f
8080 8080 7a7a 7a7a bd90 60b3 7454
8bab
difference I noticed is Linux is detecting the device id of 103Ah and
the eeprom has a device id of 1039h (this value should be correct).
This is written in some datasheet (IMHO ICH4) It means that the ROM values were
not used. I tried to help you so I read some datahsets but without any
On 03.02.2008 03:34, ron minnich wrote:
On Feb 2, 2008 5:34 PM, [EMAIL PROTECTED] wrote:
Hello,
Is there a way to run a PCI rom before the PCI bus scan runs???
Yes, we have to do this on any later geode. The LX port should give
you a hint on how it's done.
Sorry, but how are
Quoting Carl-Daniel Hailfinger [EMAIL PROTECTED]:
On 03.02.2008 03:34, ron minnich wrote:
On Feb 2, 2008 5:34 PM, [EMAIL PROTECTED] wrote:
Hello,
Is there a way to run a PCI rom before the PCI bus scan runs???
Yes, we have to do this on any later geode. The LX port should give
you a
Joe, I think Carl-Daniel is asking: where is the image for the PCI ROM
located? In BIOS flash, as it is on some systems? or on some PCI card?
If on a PCI card, that makes running it before PCI is configured more
interesting. Not impossible, just harder.
ron
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* [EMAIL PROTECTED] [EMAIL PROTECTED] [080203 02:34]:
Hello,
Is there a way to run a PCI rom before the PCI bus scan runs???
Running a _PCI_ ROM without knowing where the PCI device lives (ie.
before the _scan_) sounds impossible to me. There might be something
wrong with the approach. Why do
Quoting Stefan Reinauer [EMAIL PROTECTED]:
* [EMAIL PROTECTED] [EMAIL PROTECTED] [080203 02:34]:
Hello,
Is there a way to run a PCI rom before the PCI bus scan runs???
Running a _PCI_ ROM without knowing where the PCI device lives (ie.
before the _scan_) sounds impossible to me.
Shouldn't
[EMAIL PROTECTED] wrote:
Here is what I think the PCI rom does with the original bios:
1. powers on and enables device
2. sets up PHY registers
3. sets up it PCI config registers
4. and requests use of the PCI bridge
If I could figure out how to do #1 the rest would be fairly simple to
On 03.02.2008 17:59, [EMAIL PROTECTED] wrote:
Quoting Carl-Daniel Hailfinger [EMAIL PROTECTED]:
On 03.02.2008 03:34, ron minnich wrote:
On Feb 2, 2008 5:34 PM, [EMAIL PROTECTED] wrote:
Hello,
Is there a way to run a PCI rom before the PCI bus scan runs???
Yes,
On Feb 3, 2008 12:52 PM, Carl-Daniel Hailfinger
[EMAIL PROTECTED] wrote:
OK, so the PCI ROM is located inside the main system flash. IMO we
should invent a name for such constellations. Off-card ROM?
we pretty much named this already for VGA. It is supported in various
mainboards, via
Quoting Tom Sylla [EMAIL PROTECTED]:
[EMAIL PROTECTED] wrote:
Here is what I think the PCI rom does with the original bios:
1. powers on and enables device
2. sets up PHY registers
3. sets up it PCI config registers
4. and requests use of the PCI bridge
If I could figure out how to do #1
Yep. Take a look in pci_rom.c, there's a function that runs the rom (I think
it's just rom_run but it might be pci_rom_run). It can't go into auto.c,
since it's only in post-ram linuxbios, but there should be somewhere you can
put it (maybe i82801xx.c's i82801xx_init is early enough, or else the
On Feb 2, 2008 5:34 PM, [EMAIL PROTECTED] wrote:
Hello,
Is there a way to run a PCI rom before the PCI bus scan runs???
Yes, we have to do this on any later geode. The LX port should give
you a hint on how it's done.
Thanks
ron
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