Re: [coreboot] SPD sanity check

2009-10-26 Thread Tom Sylla
On Fri, Oct 2, 2009 at 4:07 PM, ron minnich rminn...@gmail.com wrote: Maybe it is a difference in view. The address is 7 bits in all the docs. How it is laid out in the register and on the bits on the wire is really a different concern. Sorry for the dead horse revival, but I was just looking

Re: [coreboot] SPD sanity check

2009-10-26 Thread ron minnich
On Mon, Oct 26, 2009 at 2:05 PM, Tom Sylla tsy...@gmail.com wrote: On Fri, Oct 2, 2009 at 4:07 PM, ron minnich rminn...@gmail.com wrote: Maybe it is a difference in view. The address is 7 bits in all the docs. How it is laid out in the register and on the bits on the wire is really a different

Re: [coreboot] SPD sanity check

2009-10-03 Thread Stefan Reinauer
ron minnich wrote: BTW, THANKS for the note. I was hoping for a note from an expert :-) That leading bytes sure looked like SPD but my obsolete JDEC docs threw me off. Now I wonder why I only see one SPD ... but that's grist for another note in little bit. Thanks ron What other

Re: [coreboot] SPD sanity check

2009-10-03 Thread ron minnich
I'll poll the whole smbus monday. One problem is it doesn't seem to work at all under factory bios -- Linux can't get to it. I expect the BMC is, once again, getting in the way. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] SPD sanity check

2009-10-02 Thread Joseph Smith
On Thu, 1 Oct 2009 20:39:40 -0700, ron minnich rminn...@gmail.com wrote: On Thu, Oct 1, 2009 at 6:21 PM, Joseph Smith j...@settoplinux.org wrote: That doesn't look right at all! Shouldn't your dimms be at smbus 0x50 and 0x51? What SuperIO is this? not at all, DIMMS can run from 50-57.

Re: [coreboot] SPD sanity check

2009-10-02 Thread Carl-Daniel Hailfinger
On 02.10.2009 13:29, Joseph Smith wrote: On Thu, 1 Oct 2009 20:39:40 -0700, ron minnich rminn...@gmail.com wrote: On Thu, Oct 1, 2009 at 6:21 PM, Joseph Smith j...@settoplinux.org wrote: That doesn't look right at all! Shouldn't your dimms be at smbus 0x50 and 0x51? What SuperIO is

Re: [coreboot] SPD sanity check

2009-10-02 Thread Joseph Smith
On Thu, 1 Oct 2009 20:39:40 -0700, ron minnich rminn...@gmail.com wrote: On Thu, Oct 1, 2009 at 6:21 PM, Joseph Smith j...@settoplinux.org wrote: That doesn't look right at all! Shouldn't your dimms be at smbus 0x50 and 0x51? What SuperIO is this? not at all, DIMMS can run from 50-57.

Re: [coreboot] SPD sanity check

2009-10-02 Thread Carl-Daniel Hailfinger
On 02.10.2009 13:46, Joseph Smith wrote: On Thu, 1 Oct 2009 20:39:40 -0700, ron minnich rminn...@gmail.com wrote: I think one of those SPD dumps is good, one bad, but I want to see what anyone else thinks. You know Ron you could always compare the JEDEC registers with the dimms

Re: [coreboot] SPD sanity check

2009-10-02 Thread Joseph Smith
On Fri, 02 Oct 2009 13:53:43 +0200, Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net wrote: On 02.10.2009 13:46, Joseph Smith wrote: On Thu, 1 Oct 2009 20:39:40 -0700, ron minnich rminn...@gmail.com wrote: I think one of those SPD dumps is good, one bad, but I want to see what

Re: [coreboot] SPD sanity check

2009-10-02 Thread ron minnich
OK, well, I did not quite get the answers I hoped for. So here go my comments: On Thu, Oct 1, 2009 at 5:04 PM, ron minnich rminn...@gmail.com wrote: dimm 50 00: bad device: 01 dimm 51 00: bad device: 01 dimm 52 00: bad device: 01 dimm 53 00: bad device: 01 obviously bad. dimm

Re: [coreboot] SPD sanity check

2009-10-02 Thread ron minnich
On Fri, Oct 2, 2009 at 4:53 AM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net wrote: decode-dimms (or decode-dimms.pl) from lm-sensors is extremely useful for this. Run it on a working system and it will dump the content of all SPDs and show the meaning of the values stored there.

Re: [coreboot] SPD sanity check

2009-10-02 Thread Tom Sylla
On Fri, Oct 2, 2009 at 12:53 PM, ron minnich rminn...@gmail.com wrote: On Fri, Oct 2, 2009 at 4:53 AM, Carl-Daniel Hailfinger The lm_sensors tools are handy when everything is working fine. They're not when things are not. In my case, things are not and, sadly, the tools are largely useless --

Re: [coreboot] SPD sanity check

2009-10-02 Thread ron minnich
On Fri, Oct 2, 2009 at 11:41 AM, Tom Sylla tsy...@gmail.com wrote: As a side rant, why does do Linux and coreboot insist on referring to SMBus addresses shifted right byte one bit? They are 7 bits long, and should be *left* justified in the byte. Take a look at every SMBus controller, and you

Re: [coreboot] SPD sanity check

2009-10-02 Thread ron minnich
BTW, THANKS for the note. I was hoping for a note from an expert :-) That leading bytes sure looked like SPD but my obsolete JDEC docs threw me off. Now I wonder why I only see one SPD ... but that's grist for another note in little bit. Thanks ron -- coreboot mailing list:

Re: [coreboot] SPD sanity check

2009-10-02 Thread Joseph Smith
On 10/02/2009 04:09 PM, ron minnich wrote: BTW, THANKS for the note. I was hoping for a note from an expert :-) :-( -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] SPD sanity check

2009-10-02 Thread ron minnich
On Fri, Oct 2, 2009 at 6:31 PM, Joseph Smith j...@settoplinux.org wrote: On 10/02/2009 04:09 PM, ron minnich wrote: BTW, THANKS for the note. I was hoping for a note from an expert :-) Joseph, don't feel bad; I clearly don't know much about this stuff either :-) That's why I'm glad we have

[coreboot] SPD sanity check

2009-10-01 Thread ron minnich
This looks to me like I'm mostly reading garbage from SPD -- comments anyone? dimm 50 00: bad device: 01 dimm 51 00: bad device: 01 dimm 52 00: bad device: 01 dimm 53 00: bad device: 01 dimm 54 00: ad db de c0 01 00 00 00 01 f0 fa fa 00 00 00 d9 10: 00 00 00 00 00 00 6c 01 00 00 00 00 00

Re: [coreboot] SPD sanity check

2009-10-01 Thread Joseph Smith
On 10/01/2009 08:04 PM, ron minnich wrote: This looks to me like I'm mostly reading garbage from SPD -- comments anyone? dimm 50 00: bad device: 01 dimm 51 00: bad device: 01 dimm 52 00: bad device: 01 dimm 53 00: bad device: 01 dimm 54 00: ad db de c0 01 00 00 00 01 f0 fa fa 00 00 00

Re: [coreboot] SPD sanity check

2009-10-01 Thread ron minnich
On Thu, Oct 1, 2009 at 6:21 PM, Joseph Smith j...@settoplinux.org wrote: That doesn't look right at all! Shouldn't your dimms be at smbus 0x50 and 0x51? What SuperIO is this? not at all, DIMMS can run from 50-57. I think one of those SPD dumps is good, one bad, but I want to see what anyone