Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

continuing the chat, for displaying "Hello world" on serial #define CLKIN_DEV PNP_DEV(0x2e, IT8718F_GPIO) void mainboard_romstage_entry(unsigned long bist) { ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); How can I

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Is that the one ? -rw-rw-r-- 1 bianchi bianchi 524288 Oct 16 13:04 coreboot.rom can it be uploaded as *.hex or *.bin to my flash ? my flash is W39V040FB inside /coreboot/build/ -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

I retry it without "microcode." it can compile completely, but where can I find coreboot.rom to be burn to flash chip , Debug result : bianchi@ubuntu:~/coreboot$ make menuconfig configuration written to /home/bianchi/coreboot/.config *** End of the configuration. *** Execute 'make' to start

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Why did it stop ? Any clues ? bianchi@ubuntu:~/coreboot$ make # # configuration written to /home/bianchi/coreboot/.config # CC bootblock/mainboard/intel/i946gz/static.o CC bootblock/arch/x86/boot.o GENgenerated/bootblock.ld CP

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

On 15.10.2016 15:44, Riko Ho wrote: > So I must do rm .config and make menu config then don't select : > > CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM , where is that option, may be I > did, I forget already... > Can you read it from .config ? Yes, it would have shown up as a line that says

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

So I must do rm .config and make menu config then don't select : CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM , where is that option, may be I did, I forget already... Can you read it from .config ? Anyway, what's the safe mode / default for make menuconfig ? What's the payload option should I

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Hi, On 15.10.2016 13:26, Antonius Riko wrote: > I closed the patch > > //#include > //#include > //#include > > and I got error : > > bianchi@ubuntu:~/coreboot$ make > GENgenerated/bootblock.ld > CP bootblock/arch/x86/bootblock.ld > LINK

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Thanks, for the response Here's what I've got, what else do I miss here ? I closed the patch //#include //#include //#include and I got error : bianchi at ubuntu :~/coreboot$ make GENgenerated/bootblock.ld CP

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Hi Rick, from your messages on IRC, I guess you almost got it. You have to select SOUTHBRIDGE_INTEL_I82801GX in your mainboard's Kconfig. Just do a `git grep select\ SOUTHBRIDGE_INTEL_I82801GX` and you'll find where it's set for other boards. The correct files should then be added by Makefiles.

[coreboot] southbridge/intel/i82801gx/i82801gx.h

Everyone, I tried to port I946GZ and following from 945 example on intel mainboard, and I got error when compiling : build/romstage/mainboard/intel/i946gz/romstage.o: In function `mainboard_romstage_entry': /home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:214: undefined reference to