Antony AbeePrakash X V wrote:
> This time I tried with verbose option and the output is below
> $ ./cbmem -V -t
..
> Failed to mmap /dev/mem: Operation not permitted
You have to run that command as root. Regular users are not allowed
arbitrary access to memory.
//Peter
--
coreboot mailing
rbin [mailto:adur...@google.com]
Sent: Thursday, October 11, 2018 9:44 PM
To: Antony AbeePrakash X V
Cc: Coreboot ; Dinesh Kumar
Subject: Re: [coreboot] MRC in coreboot
cbmem timstamps will be needed.
Looks like FSP is manipulating the tsc:
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 4291539104 ex
t.org>>; Dinesh
Kumar
mailto:dineshkumar.varadara...@lnttechservices.com>>
Subject: Re: [coreboot] MRC in coreboot
cbmem timstamps will be needed.
Looks like FSP is manipulating the tsc:
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 4291539104 exit 0
I have a hard time believing that
ESERVED
How old of a cbmem utility are you using? don't understand where the
1MiB mappings are coming from.
>
>
>
> Thanks,
>
> Antony
>
>
>
> From: Aaron Durbin [mailto:adur...@google.com]
> Sent: Friday, October 12, 2018 7:12 PM
> To: Antony AbeePraka
erence.
>
> Please look into this and provide feedback.
>
> Thanks,
> Antony
>
> -Original Message-
> From: Aaron Durbin [mailto:adur...@google.com]
> Sent: Thursday, October 11, 2018 7:27 PM
> To: Antony AbeePrakash X V
> Cc: Coreboot ; Dinesh Kumar <
essage-
> From: Aaron Durbin [mailto:adur...@google.com]
> Sent: Wednesday, September 05, 2018 7:39 PM
> To: Antony AbeePrakash X V
> Cc: Coreboot
> Subject: Re: [coreboot] MRC in coreboot
>
> On Wed, Sep 5, 2018 at 8:06 AM Antony AbeePrakash X V
> wrote:
> >
> >
be done further ?
Thanks,
Antony
-Original Message-
From: Aaron Durbin [mailto:adur...@google.com]
Sent: Wednesday, September 05, 2018 7:39 PM
To: Antony AbeePrakash X V
Cc: Coreboot
Subject: Re: [coreboot] MRC in coreboot
On Wed, Sep 5, 2018 at 8:06 AM Antony AbeePrakash X V
wrote
t; To: Antony AbeePrakash X V
> Cc: Coreboot ; Dinesh Kumar <
> dineshkumar.varadara...@lnttechservices.com>
> Subject: Re: [coreboot] MRC in coreboot
>
> On Thu, Oct 11, 2018 at 3:24 AM Antony AbeePrakash X V <
> antonyabee.prakas...@lnttechservices.com> wrote:
&g
in [mailto:adur...@google.com]
> Sent: Wednesday, September 05, 2018 7:39 PM
> To: Antony AbeePrakash X V
> Cc: Coreboot
> Subject: Re: [coreboot] MRC in coreboot
>
> On Wed, Sep 5, 2018 at 8:06 AM Antony AbeePrakash X V
> wrote:
> >
> > Hi,
> >
> >
On Wed, Sep 5, 2018 at 8:06 AM Antony AbeePrakash X V
wrote:
>
> Hi,
>
>
>
> We are developing coreboot for Apollo lake custom board. MRC training data
> save is enabled in FSP using Binary configuration tool.
>
>
>
> But we are getting logs like,
>
>
>
> No MRC cache found.
>
> MRC SeCUmaSize
10 matches
Mail list logo