[coreboot] Problem with USB keyboard

Hi, I'm begin with coreboot and seaBIOS. I have the problem with USB keyboard and mouse. When I boot the firmware my keyboard and mouse don't work. I use : coreboot, payload seaBios, MinnowMax board Problem: What I need to do for correct a firmware? Best regards, *Anteja * -- coreboot mailing

Re: [coreboot] coreboot community chat

Hi Stefan, thanks for organizing this! I think it's a really good idea. On 07.05.2015 06:05, Stefan Reinauer wrote: Hi coreboot community! In order to have more face time and a more personal connection with each other than it is possible on the coreboot IRC channel, I would like to invite

Re: [coreboot] Soft-Reset when enabling resources on Sun Ultra 40 M2

Hi, Sorry just a quick note, I need to go now. Usually it happens when resources assigned are wrong (like overlapping local APIC or the area ffe which is used to deliver IRQs. CHeck resource allocation. I assume your problem happens when you enable the bridge decoding. Thanks Rudolf

[coreboot] Problem with USB keyboard and mouse

Hi, I'm begin with coreboot and seaBIOS. I have the problem with USB keyboard and mouse. When I boot the firmware my keyboard and mouse don't work. I use : coreboot, payload seaBios, MinnowMax board Problem: What I need to do for correct a firmware? Best regards, *Anteja Vuk - Maček * --

Re: [coreboot] [poll] device_t

one counter-question: is romcc ever going away, or at least is the usage gong to change such that no code would ever use the uint32 version of device_t? If it's *never* going away then I think the change makes no sense. If romcc is going away, then I would favor the change. ron -- coreboot

Re: [coreboot] [poll] device_t

* ron minnich rminn...@gmail.com [150507 21:35]: one counter-question: is romcc ever going away, or at least is the usage gong to change such that no code would ever use the uint32 version of device_t?  If it's *never* going away then I think the change makes no sense. If romcc

[coreboot] [poll] device_t

Since Edward started hijacking patches on gerrit to push his agenda of getting rid of device_t without prior discussion, I would like to start a poll on how people think about this, and maybe find reasons for why it might be a good idea. Edward wrote: The issue of 'device_t' has many heads. The

Re: [coreboot] [poll] device_t

2015-05-07 22:00 GMT+02:00 Stefan Reinauer stefan.reina...@coreboot.org: With our current bootblock concept, it is never going away on x86 (for bootblock usage) Which isn't that much of a problem once we provide separate headers for x86 bootblock code. There's really very tiny overlap. That

[coreboot] ASUS KFSN4-DRE Automated Test Failure

The ASUS KFSN4-DRE fails verification as of commit b2aee6f2e7c61ae87ddfdab00c22775313603981 The following tests failed: CBMEM_OBJECT_TABLE_TRUNCATED Commits since last successful test: b2aee6f vboot2: Replace hard coded 'fallback' prefix with Kconfig variable b4a6ca9 imgtec/pistachio: Add

Re: [coreboot] AGESA PI for Olivehill+

Hello Wolfgang, It is correct that you can't use this right away but the memory configurations can be made. We have done this for several FT3B SoC based boards. We can do this for your board as well. Please contact me off-line if you are interested. Best Regards, Wim Vervoorn

[coreboot] AGESA PI for Olivehill+

Hi Bruce, is it right that the AGESA Pi binary for AMD Olivehill+ board is not usable for custom board implementations of FT3B GSOC? For example, if we use memory down design in star topology, AGESA will fail to initialize DDR3. Regards, Wolfgang -- coreboot mailing list:

Re: [coreboot] Problem with USB keyboard

On 2015-05-07 11:25, Anteja Vuk-Maček wrote: Hi, I'm begin with coreboot and seaBIOS. I have the problem with USB keyboard and mouse. When I boot the firmware my keyboard and mouse don't work. I use : coreboot, payload seaBios, MinnowMax board Problem: What I need to do for correct a firmware?

Re: [coreboot] AGESA PI for Olivehill+

On to, 2015-05-07 at 13:19 +, Wolfgang Kamp - datakamp wrote: Hi Bruce, is it right that the AGESA Pi binary for AMD Olivehill+ board is not usable for custom board implementations of FT3B GSOC? For example, if we use memory down design in star topology, AGESA will fail to initialize