Re: [coreboot] About Paging, Realmode and what is going on

On Mon, Sep 4, 2017 at 3:41 PM Philipp Stanner wrote: > > Start the board, load the OS and go back into your flash until reboot. > Just checking, but have you looked at the code to see what "start the board" really means? Hint: on x86 it's essentially one billion instructions

Re: [coreboot] What GPU are you using on KGPE-D16

On 09/04/2017 10:44 PM, Iru Cai wrote: Hi, I've just flashed the most recent coreboot with Linux payload on my KGPE-D16. However, there're some problems with GPU. I have an RX550, but it seems that amdgpu has bug with AMD-Vi which I found in some mailing list (), and it still doesn't work

[coreboot] What GPU are you using on KGPE-D16

Hi, I've just flashed the most recent coreboot with Linux payload on my KGPE-D16. However, there're some problems with GPU. I have an RX550, but it seems that amdgpu has bug with AMD-Vi which I found in some mailing list ( https://lists.freedesktop.org/archives/amd-gfx/2017-March/006490.html),

Re: [coreboot] [flashrom] Erase failure on Sapphire Pure Platinum H61 with coreboot

September 3, 2017 12:24 AM, "Nico Huber" wrote: > TLDR; it would be a lot slower. > > Alas, there is no usual byte-program mode. Most chips do a 256B page > program which uses op code 0x02 too. For the SST25VF032B it's really a > 1B program. If you use that instead of the AAI

Re: [coreboot] About Paging, Realmode and what is going on

> But a bootloader built as a payload could also be built to use BIOS > interfaces. GRUB is one example of this. Let us assume the following configuration: FSP -> Coreboot -> Payload: GRUB2 -> Linux No legacy interrupts, correct? So, what is this for the architecture? CSM? UEFI look alike? I

Re: [coreboot] Boot from a M.2 NVMe ssd on an ASUS KGPE-D16

On Mon, Sep 4, 2017 at 3:47 PM, BogDan Vatra wrote: > Hi, > > Is it possible to boot from a M.2 NVMe ssd on KGPE-D16? > If not, how hard it will be to add such support, I'd like to give it a > try myself. > > I'm using Linux kernel payload with petitboot. Now SeaBIOS also

Re: [coreboot] About Paging, Realmode and what is going on

Thanks so far. Very interesting. Am Montag, den 04.09.2017, 07:28 + schrieb Peter Stuge: > > coreboot itself can only start one payload, but SeaBIOS allows the > user to choose which of those payloads to start, in which case a > payload *does* have interrupt services available. > > Just to

Re: [coreboot] Boot from a M.2 NVMe ssd on an ASUS KGPE-D16

On 09/04/2017 03:56 AM, taii...@gmx.com wrote: On 09/04/2017 03:47 AM, BogDan Vatra wrote: Hi, Is it possible to boot from a M.2 NVMe ssd on KGPE-D16? If not, how hard it will be to add such support, I'd like to give it a try myself. Yours, BogDan. Use the grub payload instead of the

[coreboot] Boot from a M.2 NVMe ssd on an ASUS KGPE-D16

Hi, Is it possible to boot from a M.2 NVMe ssd on KGPE-D16? If not, how hard it will be to add such support, I'd like to give it a try myself. Yours, BogDan. -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Boot from a M.2 NVMe ssd on an ASUS KGPE-D16

On 09/04/2017 03:47 AM, BogDan Vatra wrote: Hi, Is it possible to boot from a M.2 NVMe ssd on KGPE-D16? If not, how hard it will be to add such support, I'd like to give it a try myself. Yours, BogDan. Use the grub payload instead of the SeaBIOS payload. (directions on how to add a grub

Re: [coreboot] Boot from a M.2 NVMe ssd on an ASUS KGPE-D16

Hi, But grub doesn't see it at all (I boot grub from another hdd to check it :) ) BogDan. 2017-09-04 10:56 GMT+03:00 taii...@gmx.com : > On 09/04/2017 03:47 AM, BogDan Vatra wrote: > >> Hi, >> >> Is it possible to boot from a M.2 NVMe ssd on KGPE-D16? >> If not, how hard it

Re: [coreboot] Boot from a M.2 NVMe ssd on an ASUS KGPE-D16

On 09/04/2017 03:59 AM, BogDan Vatra wrote: Hi, But grub doesn't see it at all (I boot grub from another hdd to check it :) ) BogDan. Hmm what devices does grub see and what version are you using? -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] INT 13, real mode, block write commands and coreboot

> is there a way to disable this BIOS function? More precisely, coreboot can be set to avoid > receiving commands from GRUB and Ubuntu KERNEL? If you build the following structure (please, do understand that this is very high level of presentation, which does not reflect reality 100%) on x86

Re: [coreboot] About Paging, Realmode and what is going on

Philipp Stanner wrote: > Once coreboot jumped into SeaBIOS-code the latter is responsible for > providing the right interface for interrupt services. Sure, coreboot does not provide interrupt services. I did not mean to claim that it does. Sorry if there was confusion. > I guess it doesn't

Re: [coreboot] About Paging, Realmode and what is going on

Zoran Stojsavljevic wrote: > > But a bootloader built as a payload could also be built to use BIOS > > interfaces. GRUB is one example of this. > > Let us assume the following configuration: > FSP -> Coreboot -> Payload: GRUB2 -> Linux > > No legacy interrupts, correct? Correct. > So, what is

Re: [coreboot] About Paging, Realmode and what is going on

Peter Stuge wrote: > The MBR is irrelevant in the above scenario, it is never read. .. > The payload directly reads the filesystem from disk, no boot sector is used. To clarify, I mean code here. No code is read/loaded/used from MBR. The partition table is read, but I expect that GRUB2 supports

Re: [coreboot] About Paging, Realmode and what is going on

Am Montag, den 04.09.2017, 20:15 + schrieb Peter Stuge: > legacy > tables such as ACPI ACPI is a open standard, isn't it? > > The payload directly reads the filesystem from disk, no boot sector > is used. Indeed. So a payload built for cb won't try to call BIOS. And if something after it

Re: [coreboot] About Paging, Realmode and what is going on

> Hint: on x86 it's essentially one billion instructions before you can even think about using RAM, much less loading the payload. This is why everybody using INTEL silicon do have FSP as A MUST (instead SEC+PEI). And this is why CORE CPU creations (2C+) have > 500 million gates per silicon.