Re: [coreboot] Ram Init: Intel i945: Timing parameters

Mohit Gupta wrote: > wondering how coreboot team was able to write i945 ram init? The code was written by individuals who had limited access to Intel documents and source code under NDA. Those individuals can not tutor you in the i945 MCH or in DDR2 technology. //Peter -- coreboot mailing li

Re: [coreboot] Ram Init: Intel i945: Timing parameters

Thanks Vald … not possible to break intel safe .. wondering how coreboot team was able to write i945 ram init? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Ram Init: Intel i945: Timing parameters

Thanks Vald … not possible to break intel safe .. wondering how coreboot team was able to write i945 ram init?   Regards Mohit Gupta On Friday, 14 February 2014 10:39 AM, Vladimir 'φ-coder/phcoder' Serbinenko wrote: On 14.02.2014 00:03, Mohit Gupta wrote: >> I am having trouble understan

Re: [coreboot] Ram Init: Intel i945: Timing parameters

On Friday, February 14, 2014 12:38:58 AM Vladimir 'φ-coder/phcoder' Serbinenko wrote: > Sure: > 1) Locate intel offices > 2) Locate their top-secret safes > 3) Observe security > 4) Buy military gear > 5) Recruit and train a company (~200 people) for a year > 6) Launch assault on the office > 7) B

Re: [coreboot] Ram Init: Intel i945: Timing parameters

On 14.02.2014 00:03, Mohit Gupta wrote: > I am having trouble understanding i945 ram init code especially timing > parameters. Can some explain me in layman language? When I go through > DDR2 specification, timing related text is too complex and confusing. > Interested in getting very simple explan

Re: [coreboot] Ram-init: Intel

Thanks Peter for your support. I will have a look at provided links.  Regards Mohit Gupta-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] coreboot port for macbook2,1

On 13.02.2014 23:47, Mono wrote: > Hallo > > finally I managed to enable SPI on the Beaglebone Black and use it as > external programmer with flashrom. > I read the macbook's flash chip twice, as suggested. Both rom files are > identical. But: a few days/week ago I read the flash chip with the m

[coreboot] Ram Init: Intel i945: Timing parameters

I am having trouble understanding i945 ram init code especially timing parameters. Can some explain me in layman language? When I go through DDR2 specification, timing related text is too complex and confusing. Interested in getting very simple explanation. Also, i945 ram init code is doing lot

[coreboot] How do I reply to a post?

  Regards Mohit Gupta-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] coreboot port for macbook2,1

Hallo finally I managed to enable SPI on the Beaglebone Black and use it as external programmer with flashrom. I read the macbook's flash chip twice, as suggested. Both rom files are identical. But: a few days/week ago I read the flash chip with the macbook's internal programmer. This file diff

Re: [coreboot] Fwd: IMB-A180E H coreboot won't boot (new)

I thought the instructions from the coreboot HOWTO web page would give me the latest code. The git log command (below) did show recent changes, but when I "cd coreboot; git pull", none of them came down. What is the command to update src/mainboard/asrock/imb-a180? Thanks, Mark On 02/13/2014

Re: [coreboot] Fwd: IMB-A180E H coreboot won't boot (new)

On 02/13/2014 07:58 PM, Mark C. Mason wrote: I'm new to coreboot, and I'm working to use it with an ASROCK IMB-A180, the H version with the LVDS port. Hey You seem to build with coreboot source from Aug 2013. There has been several changes affecting this board since then, some more critical

Re: [coreboot] SeaVGABIOS with native vga init (Need testers)

On Thu, Feb 13, 2014 at 10:24:21AM +0100, Vladimir 'φ-coder/phcoder' Serbinenko wrote: > On 13.02.2014 01:23, Kevin O'Connor wrote: > >> Looking through the output of > >> > > >> > $ git grep k8t890 src/mainboard/ > >> > > >> > the boards Asus A8V-E Deluxe, Asus A8V-E SE, Asus K8V-X, Asus M2V-M

Re: [coreboot] Alias motherboard?

It's not supported until you can run the script on the node that shows it booted. We've gotten away from just saying "this is like that so it must work." Run the script. That's the requirement now. ron On Thu, Feb 13, 2014 at 5:23 AM, Oskar Enoksson wrote: > I noticed that "AMD Serenade" mot

[coreboot] Alias motherboard?

I noticed that "AMD Serenade" motherboard is not listed as supported. However, supposedly that motherboard is identical to HP DL145 G1. So, probably using the hp/dl145_g1 motherboard configuration will produce a ROM that works with "AMD Serenade" aswell. Are such alias motherboards handled in any

Re: [coreboot] Ram-init: Intel i945: sdram_detect_cas_latency_and_ram_speed

Mohit Gupta wrote: > I am trying to understand ram initialization process for intel i945 chipset. > Would some be able to guide me as what sdram_detect_cas_latency_and_ram_speed > is trying to do. I am a newbie, hence, entitled to ask stupid question :) Being a newbie is fine, asking too simple qu

Re: [coreboot] Trouble with coreboot for Roda RK9

Hello Dmitry, > Why can't I read the condition GP1 - GP4? > When I start the program superiotool with original bios, it shows regular > results, when I start the program superiotool with coreboot the program > shows 0 at GP1-GP4. It is in GP4 the DIP switcher locates to chose the > type of LCD. I

Re: [coreboot] SeaVGABIOS with native vga init (Need testers)

On 13.02.2014 01:23, Kevin O'Connor wrote: >> Looking through the output of >> > >> >$ git grep k8t890 src/mainboard/ >> > >> > the boards Asus A8V-E Deluxe, Asus A8V-E SE, Asus K8V-X, Asus M2V-MX SE >> > and Asus M2V should theoretically support that. > Okay. The SeaVGABIOS implementation i