Re: [coreboot] GPL license headers

2015-10-22 Thread Stefan Reinauer 
>From my previous discussions with lawyers on the topic, the third
paragraph is unproblematic to remove. With resolutions of today's
monitors and keyboards often having a page down key, keeping the second
paragraph seems like a good compromise to stay friends with the legal
experts and err on the safe side.

Stefan

* ron minnich  [151021 05:41]:
> Let me ask around.
> 
> ron
> 
> On Tue, Oct 20, 2015 at 7:20 PM Martin Roth  wrote:
> 
> I haven't seen any disagreement that we get rid of the entire third
> paragraph.
> 
> Alex votes that we should get rid of the second paragraph of the
> header as well, and what Ron posted SEEMS to support that we can,
> although the wording in that license header might be different enough
> that it doesn't apply to our case.
> 
> Personally, I'm in favor of keeping the second paragraph.  It looks to
> me like the first paragraph just discusses distribution, not
> liability.  I don't really see any NEED to get rid of the second
> paragraph.
> 
> Are there any other thoughts either way on getting rid of the second
> paragraph?
> 
> Martin
> 
> 
> 
> On Tue, Oct 20, 2015 at 6:47 PM, Alex G.  wrote:
> > On 10/20/2015 10:54 AM, ron minnich wrote:
> >> Eben Moglen, who ought to know, guided us on the release rules for the
> >> Plan 9 GPL release.
> >>
> >> Here is what he told us could go in each file:
> >> /*
> >>  * This file is part of the UCB release of Plan 9. It is subject to the
> >> license
> >>  * terms in the LICENSE file found in the top-level directory of this
> >>  * distribution and at 
> http://akaros.cs.berkeley.edu/files/Plan9License.
> No
> >>  * part of the UCB release of Plan 9, including this file, may be
> copied,
> >>  * modified, propagated, or distributed except according to the terms
> >> contained
> >>  * in the LICENSE file.
> >>  */
> >
> > +2
> >
> >> On Tue, Oct 20, 2015 at 10:30 AM Patrick Georgi  >> > wrote:
> >>     Get (the right set of) lawyers to sign off on that.
> >
> > You were saying, Patrick?
> >
> > Alex
> >
> > --
> > coreboot mailing list: coreboot@coreboot.org
> > http://www.coreboot.org/mailman/listinfo/coreboot
> 

> -- 
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


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[coreboot] New on blogs.coreboot.org: coreboot changelog

2015-10-22 Thread WordPress 
A new post titled "coreboot changelog" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2015/10/22/coreboot-changelog-3/

This report covers commits b66d673..d98471c, the week up to Sunday, 2015-10-18
This week has an interesting distribution in its commits: A few very large and impactful commits (and commit sets), but otherwise lots of tiny little things. The last months typically saw more cohesive changes each week, affecting a small number of subsystems or drivers – but not this week.
The biggest item in terms of code size was the reintroduction of Intel’s Rangeley SoC and related mainboard, which were found to still be requested by users after all.
The biggest item in terms of impact was probably the improvement of our automated build testing by adding our lint tests and build tests for various utilities to our build infrastructure, reporting any errors (and preventing them from creeping into the master branch). We don’t test all tools yet, but adding the others should be painless now. libpayload also gained a new test configuration so both libcurses implementations are now covered.
The vboot verstage concept was ported to x86 and added to FSP 1.1, allowing a separate verification stage to check romstage before executing it (from a potentially unsafe location).
AMD microcode can now be loaded from CBFS, and using their standard format instead of a custom layout that was used by coreboot until now.
Apart from these, changes happened all across the tree:
SMBIOS tables report memory vendors; ACPI was cleaned up to work better with new ACPI compiler versions; there’s better reporting for MTRR configurations, and related macros have more sensible names; the ARMv7 code avoids miscompilation with gcc-5.2, which is significant because that’s our standard compiler version; Intel GMA ACPI saw improvements; there were tons of style fixes in preparation to deal with the addition of lint tests to the automated tests; cbfstool can now add files after files of the same name were removed from an image; the coreinfo payload has the sense to reboot after it’s done; the cbmem utility is more robust, and several more cleanups and bugfixes.


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[coreboot] Asus M2N-E no boot, post codes A5 80 73

2015-10-22 Thread Balázs Vinarz 
Hi.
I compiled from the source about 6 months and now. The mobo is still unable
to boot.
Serial debugs are attached, i tried with many memory-modules in all sockets.
There are two options, when the postcard jumps between codes A5 and 80:

#START
coreboot-4.1-781-g744729a Tue Oct 20 14:50:25 UTC 2015 romstage starting...

*sysinfo range: [000c8020,000c8750]

bsp_apicid=0x00

Enabling routing table for node 0 done.

Enabling UP settings

Disabling read/write/fill probes for UP... done.

coherent_ht_finalize

done

core0 started:

started ap apicid:

SBLink=00

NC node|link=00

entering optimize_link_incoherent_ht

sysinfo->link_pair_num=0x1

entering ht_optimize_link

pos=0x8a, unfiltered freq_cap=0x8075

pos=0x8a, filtered freq_cap=0x75

pos=0x52, unfiltered freq_cap=0x7f

pos=0x52, filtered freq_cap=0x7f

freq_cap1=0x75, freq_cap2=0x7f

dev1 old_freq=0x6, freq=0x6, needs_reset=0x0

dev2 old_freq=0x6, freq=0x6, needs_reset=0x0

width_cap1=0x11, width_cap2=0x11

dev1 input ln_width1=0x4, ln_width2=0x4

dev1 input width=0x1

dev1 output ln_width1=0x4, ln_width2=0x4

dev1 input|output width=0x11

old dev1 input|output width=0x11

dev2 input|output width=0x11

old dev2 input|output width=0x11

after ht_optimize_link for link pair 0, reset_needed=0x0

after optimize_link_read_pointers_chain, reset_needed=0x0

mcp55_num: 01

Ram1.00

setting up CPU 00 northbridge registers

done.

Ram2.00

sdram_set_spd_registers: paramx :000cff38

Unbuffered

333MHz

333MHz

Interleaving disabled

RAM end at 0x0010 kB

Ram3

Initializing memory:  done

Setting variable MTRR 2, base:0MB, range: 1024MB, type WB

set DQS timing:RcvrEn:Pass1: 00

 CTLRMaxDelay=ae

Total DQS Training : tsc [00]=12a29d35

Total DQS Training : tsc [01]=4d330002

Total DQS Training : tsc [02]=7a48

Total DQS Training : tsc [03]=fff85d4d0064

Ram4

Prepare CAR migration and stack regions... Fill [001ff400-001f] ...
Done
Copying data from cache to RAM...  Copy [000c8000-000c877f] to [001ff880 -
001fe
Switching to use RAM as stack...





INIT detected from  --- { APICID = 00 NODEID = 00 COREID = 00} ---



Issuing SOFT_RESET...

coreboot-4.1-781-g744729a Tue Oct 20 14:50:25 UTC 2015 romstage starting...

*sysinfo range: [000c8020,000c8750]

bsp_apicid=0x00

Enabling routing table for node 0 done.

Enabling UP settings

Disabling read/write/fill probes for UP... done.

coherent_ht_finalize

done

core0 started:

started ap apicid:

SBLink=00

NC node|link=00

entering optimize_link_incoherent_ht

sysinfo->link_pair_num=0x1

entering ht_optimize_link

pos=0x8a, unfiltered freq_cap=0x8075

pos=0x8a, filtered freq_cap=0x75

pos=0x52, unfiltered freq_cap=0x7f

pos=0x52, filtered freq_cap=0x7f

freq_cap1=0x75, freq_cap2=0x7f

dev1 old_freq=0x6, freq=0x6, needs_reset=0x0

dev2 old_freq=0x6, freq=0x6, needs_reset=0x0

width_cap1=0x11, width_cap2=0x11

dev1 input ln_width1=0x4, ln_width2=0x4

dev1 input width=0x1

dev1 output ln_width1=0x4, ln_width2=0x4

dev1 input|output width=0x11

old dev1 input|output width=0x11

dev2 input|output width=0x11

old dev2 input|output width=0x11

after ht_optimize_link for link pair 0, reset_needed=0x0

after optimize_link_read_pointers_chain, reset_needed=0x0

mcp55_num: 01

Ram1.00

setting up CPU 00 northbridge registers

done.

Ram2.00

sdram_set_spd_registers: paramx :000cff38

Unbuffered

333MHz

333MHz

Interleaving disabled

RAM end at 0x0010 kB

Ram3

Initializing memory:  done

Setting variable MTRR 2, base:0MB, range: 1024MB, type WB

set DQS timing:RcvrEn:Pass1: 00

 CTLRMaxDelay=ae

Total DQS Training : tsc [00]=12a29d35

Total DQS Training : tsc [01]=4d330002

Total DQS Training : tsc [02]=7a48

Total DQS Training : tsc [03]=fff85d4d0064

Ram4

Prepare CAR migration and stack regions... Fill [001ff400-001f] ...
Done
Copying data from cache to RAM...  Copy [000c8000-000c877f] to [001ff880 -
001fe
Switching to use RAM as stack...





INIT detected from  --- { APICID = 00 NODEID = 00 COREID = 00} ---



Issuing SOFT_RESET...

#END

And when it turn off and ends with postcode 73:

#START

ENDS WITH post 73

coreboot-4.1-781-g744729a Tue Oct 20 14:50:25 UTC 2015 romstage starting...
*sysinfo range: [000c8020,000c8750]
bsp_apicid=0x00
Enabling routing table for node 0 done.
Enabling UP settings
Disabling read/write/fill probes for UP... done.
coherent_ht_finalize
done
core0 started:
started ap apicid:
SBLink=00
NC node|link=00
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x807f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11

Re: [coreboot] GPL license headers

2015-10-22 Thread Alex G. 
On 10/22/2015 11:00 AM, Stefan Reinauer wrote:
> From my previous discussions with lawyers on the topic, the third
> paragraph is unproblematic to remove.

> With resolutions of today's monitors 

And if you're running a 4k screen, do you really want $100 of
real-estate being occupied by boilerplate? (Those monitors aren't cheap)

> and keyboards often having a page down key,

My macbookpro doesn't have a PgDn key.

> keeping the second
> paragraph seems like a good compromise to stay friends with the legal
> experts and err on the safe side.

(Realistic) sarcasm aside, I am sensitive to the legal concerns, and I
do agree with Patrick's concern that we should do our due diligence to
make sure we don't break lawyer's tools. That being said, I think we can
all agree that taking 'licensecheck' as the lowest common denominator is
not unreasonable.

Considering that this lowest common denominator has no issues
identifying the terms with just the first paragraph, a human being
should have no problem with this. I think it's worth the extra effort to
simplify the headers, and ultimately focus on coding, not boilerplating.
I'd also like to see a short (one to three lines) description of _what_
a file does above the license headers.

Alex

> Stefan
> 
> * ron minnich  [151021 05:41]:
>> Let me ask around.
>>
>> ron
>>
>> On Tue, Oct 20, 2015 at 7:20 PM Martin Roth  wrote:
>>
>> I haven't seen any disagreement that we get rid of the entire third
>> paragraph.
>>
>> Alex votes that we should get rid of the second paragraph of the
>> header as well, and what Ron posted SEEMS to support that we can,
>> although the wording in that license header might be different enough
>> that it doesn't apply to our case.
>>
>> Personally, I'm in favor of keeping the second paragraph.  It looks to
>> me like the first paragraph just discusses distribution, not
>> liability.  I don't really see any NEED to get rid of the second
>> paragraph.
>>
>> Are there any other thoughts either way on getting rid of the second
>> paragraph?
>>
>> Martin
>>
>>
>>
>> On Tue, Oct 20, 2015 at 6:47 PM, Alex G.  wrote:
>> > On 10/20/2015 10:54 AM, ron minnich wrote:
>> >> Eben Moglen, who ought to know, guided us on the release rules for the
>> >> Plan 9 GPL release.
>> >>
>> >> Here is what he told us could go in each file:
>> >> /*
>> >>  * This file is part of the UCB release of Plan 9. It is subject to 
>> the
>> >> license
>> >>  * terms in the LICENSE file found in the top-level directory of this
>> >>  * distribution and at 
>> http://akaros.cs.berkeley.edu/files/Plan9License.
>> No
>> >>  * part of the UCB release of Plan 9, including this file, may be
>> copied,
>> >>  * modified, propagated, or distributed except according to the terms
>> >> contained
>> >>  * in the LICENSE file.
>> >>  */
>> >
>> > +2
>> >
>> >> On Tue, Oct 20, 2015 at 10:30 AM Patrick Georgi > >> > wrote:
>> >> Get (the right set of) lawyers to sign off on that.
>> >
>> > You were saying, Patrick?
>> >
>> > Alex
>> >
>> > --
>> > coreboot mailing list: coreboot@coreboot.org
>> > http://www.coreboot.org/mailman/listinfo/coreboot
>>
> 
>> -- 
>> coreboot mailing list: coreboot@coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
> 

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