[coreboot] W39V040FB and W39V040FC?

Everyone, Is W39V040FB compatible with W39V040FC ? Cheers -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Is that the one ? -rw-rw-r-- 1 bianchi bianchi 524288 Oct 16 13:04 coreboot.rom can it be uploaded as *.hex or *.bin to my flash ? my flash is W39V040FB inside /coreboot/build/ -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

I retry it without "microcode." it can compile completely, but where can I find coreboot.rom to be burn to flash chip , Debug result : bianchi@ubuntu:~/coreboot$ make menuconfig configuration written to /home/bianchi/coreboot/.config *** End of the configuration. *** Execute 'make' to start

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Why did it stop ? Any clues ? bianchi@ubuntu:~/coreboot$ make # # configuration written to /home/bianchi/coreboot/.config # CC bootblock/mainboard/intel/i946gz/static.o CC bootblock/arch/x86/boot.o GENgenerated/bootblock.ld CP

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

On 15.10.2016 15:44, Riko Ho wrote: > So I must do rm .config and make menu config then don't select : > > CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM , where is that option, may be I > did, I forget already... > Can you read it from .config ? Yes, it would have shown up as a line that says

Re: [coreboot] ARMv8 prototype in simulator failing at payload_load()

Julius, I appreciate the background on the API change and the pointer to what to fix in the code. I have stubbed out the soc chip operations and now am letting coreboot know that there is a region of dram. The simulation train continues. Cheers, T.mike On 2016-10-13 14:30, Julius Werner wrote:

Re: [coreboot] Attempt to porting coreboot to Gigabyte ga-945gcm-s2l

Nico Huber writes: > Hi Arthur, > > > This is just a synchronization point. The wbinvd() is there to ensure > that the memcpy() above has reached real RAM before the program con- > tinues. > > As this fails right after resources have been assigned to all devices, I >

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

So I must do rm .config and make menu config then don't select : CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM , where is that option, may be I did, I forget already... Can you read it from .config ? Anyway, what's the safe mode / default for make menuconfig ? What's the payload option should I

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Hi, On 15.10.2016 13:26, Antonius Riko wrote: > I closed the patch > > //#include > //#include > //#include > > and I got error : > > bianchi@ubuntu:~/coreboot$ make > GENgenerated/bootblock.ld > CP bootblock/arch/x86/bootblock.ld > LINK

Re: [coreboot] Official builds for EoL Chromebooks

Yes, I think in this case you're mixing your alternate realities. No, no direct association. On 15/10/16 11:44, Zoran Stojsavljevic wrote: > Hello John, > > I'll investigate this in depth... Somehow, I remember, you were > connected with them (anyhow - as free lancer, or in different way), >

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Thanks, for the response Here's what I've got, what else do I miss here ? I closed the patch //#include //#include //#include and I got error : bianchi at ubuntu :~/coreboot$ make GENgenerated/bootblock.ld CP

Re: [coreboot] Official builds for EoL Chromebooks

Hello John, I'll investigate this in depth... Somehow, I remember, you were connected with them (anyhow - as free lancer, or in different way), aren't you? ;-) Maybe I am just too old dummy cat, and I mix virtual realities... Everything is possible! I admit. Thank you, Zoran On 10/15/16, John

[coreboot] TALOS secure workstation campaign has launched

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 Hello everyone, Here: https://www.crowdsupply.com/raptor-computing-systems/talos-secure-workst ation This is a high-end desktop/workstation, on par with Intel in terms of performance, and it's going to ship with entirely libre software on it,

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

Hi Rick, from your messages on IRC, I guess you almost got it. You have to select SOUTHBRIDGE_INTEL_I82801GX in your mainboard's Kconfig. Just do a `git grep select\ SOUTHBRIDGE_INTEL_I82801GX` and you'll find where it's set for other boards. The correct files should then be added by Makefiles.

Re: [coreboot] Official builds for EoL Chromebooks

On 13/10/16 20:45, Zoran Stojsavljevic wrote: > > John Lewis has some upstream firmware for the older > SandyBridge/IvyBridge models, > > but his Haswell firmware is build from Google's tree/branches not > upstream. > > He also has no plans for any future upstream firmware. > > Once upon a time

[coreboot] southbridge/intel/i82801gx/i82801gx.h

Everyone, I tried to port I946GZ and following from 945 example on intel mainboard, and I got error when compiling : build/romstage/mainboard/intel/i946gz/romstage.o: In function `mainboard_romstage_entry': /home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:214: undefined reference to