[coreboot] W39V040FB and W39V040FC?

[Antonius Riko]

Everyone,

Is W39V040FB compatible with W39V040FC ?
Cheers
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Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

[Antonius Riko]

Is that the one ?
-rw-rw-r--   1 bianchi bianchi 524288 Oct 16 13:04 coreboot.rom

can it be uploaded as *.hex or *.bin to my flash ? my flash is W39V040FB

inside /coreboot/build/
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Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

[Antonius Riko]

I retry it without "microcode." it can compile completely, but where
can I find coreboot.rom to be burn to flash chip ,

Debug result :
bianchi@ubuntu:~/coreboot$ make menuconfig
configuration written to /home/bianchi/coreboot/.config

*** End of the configuration.
*** Execute 'make' to start the build or try 'make help'.

bianchi@ubuntu:~/coreboot$ make
#
# configuration written to /home/bianchi/coreboot/.config
#
build/auto.conf:1974:warning: override: reassigning to symbol
CONSOLE_SERIAL_TEGRA210_UART_CHOICES
CC bootblock/mainboard/intel/i946gz/static.o
CC bootblock/arch/x86/boot.o
GENgenerated/bootblock.ld
CP bootblock/arch/x86/bootblock.ld
ROMCC  generated/bootblock.inc
CC bootblock/arch/x86/bootblock_romcc.o
CC bootblock/arch/x86/cpu_common.o
CC bootblock/arch/x86/id.o
CC bootblock/arch/x86/memcpy.o
CC bootblock/arch/x86/memset.o
CC bootblock/arch/x86/mmap_boot.o
CC bootblock/arch/x86/walkcbfs.o
CC bootblock/commonlib/cbfs.o
CC bootblock/commonlib/lz4_wrapper.o
CC bootblock/commonlib/mem_pool.o
CC bootblock/commonlib/region.o
CC bootblock/console/die.o
CC bootblock/console/post.o
CC bootblock/cpu/x86/lapic/boot_cpu.o
CC bootblock/cpu/x86/mtrr/earlymtrr.o
CC bootblock/device/device_simple.o
CC bootblock/device/i2c.o
CC bootblock/drivers/uart/uart8250io.o
CC bootblock/drivers/uart/util.o
CC bootblock/lib/boot_device.o
CC bootblock/lib/bootmode.o
FMAP   build/util/cbfstool/fmaptool -h build/fmap_config.h
build/fmap.fmd build/fmap.fmap
SUCCESS: Wrote 182 bytes to file 'build/fmap.fmap' (and generated header)
The sections containing CBFSes are: COREBOOT
CC bootblock/lib/cbfs.o
CC bootblock/lib/cbmem_console.o
CC bootblock/lib/delay.o
CC bootblock/lib/fmap.o
CC bootblock/lib/gcc.o
CC bootblock/lib/halt.o
CC bootblock/lib/hexdump.o
CC bootblock/lib/libgcc.o
CC bootblock/lib/memchr.o
CC bootblock/lib/memcmp.o
CC bootblock/lib/prog_loaders.o
CC bootblock/lib/prog_ops.o
CC bootblock/lib/version.o
CC bootblock/vboot/bootmode.o
LINK   cbfs/fallback/bootblock.debug
OBJCOPYcbfs/fallback/bootblock.elf
OBJCOPYbootblock.raw.bin
CC romstage/mainboard/intel/i946gz/static.o
CC romstage/arch/x86/acpi_s3.o
CC romstage/arch/x86/assembly_entry.o
CC romstage/arch/x86/boot.o
CC romstage/arch/x86/cbfs_and_run.o
CC romstage/arch/x86/cbmem.o
CC romstage/arch/x86/cpu_common.o
CC romstage/arch/x86/memcpy.o
CP romstage/arch/x86/memlayout.ld
CC romstage/arch/x86/memmove.o
CC romstage/arch/x86/memset.o
CC romstage/arch/x86/mmap_boot.o
CC romstage/arch/x86/postcar_loader.o
CC romstage/commonlib/cbfs.o
CC romstage/commonlib/lz4_wrapper.o
CC romstage/commonlib/mem_pool.o
CC romstage/commonlib/region.o
CC romstage/console/console.o
CC romstage/console/die.o
CC romstage/console/init.o
CC romstage/console/post.o
CC romstage/console/printk.o
CC romstage/console/vtxprintf.o
CC romstage/cpu/intel/car/romstage.o
CC romstage/cpu/intel/microcode/microcode.o
CC romstage/cpu/x86/car.o
CC romstage/cpu/x86/lapic/apic_timer.o
CC romstage/cpu/x86/lapic/boot_cpu.o
CC romstage/cpu/x86/mtrr/earlymtrr.o
CC romstage/device/device_simple.o
CC romstage/device/i2c.o
CC romstage/device/pci_early.o
CC romstage/drivers/pc80/rtc/mc146818rtc.o
CC romstage/drivers/pc80/rtc/mc146818rtc_early.o
CC romstage/drivers/uart/uart8250io.o
CC romstage/drivers/uart/util.o
CC romstage/lib/boot_device.o
CC romstage/lib/bootmode.o
CC romstage/lib/cbfs.o
CC romstage/lib/cbmem_common.o
CC romstage/lib/cbmem_console.o
CC romstage/lib/compute_ip_checksum.o
CC romstage/lib/delay.o
CC romstage/lib/fmap.o
CC romstage/lib/gcc.o
CC romstage/lib/halt.o
CC romstage/lib/hexdump.o
CC romstage/lib/imd.o
CC romstage/lib/imd_cbmem.o
CC romstage/lib/libgcc.o
CC romstage/lib/memchr.o
CC romstage/lib/memcmp.o
CC romstage/lib/memrange.o
CC romstage/lib/prog_loaders.o
CC romstage/lib/prog_ops.o
CP romstage/lib/program.ld
CC 

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

[Antonius Riko]

Why did it stop ?
Any clues ?

bianchi@ubuntu:~/coreboot$ make
#
# configuration written to /home/bianchi/coreboot/.config
#
CC bootblock/mainboard/intel/i946gz/static.o
CC bootblock/arch/x86/boot.o
GENgenerated/bootblock.ld
CP bootblock/arch/x86/bootblock.ld
ROMCC  generated/bootblock.inc
CC bootblock/arch/x86/bootblock_romcc.o
CC bootblock/arch/x86/cpu_common.o
CC bootblock/arch/x86/id.o
CC bootblock/arch/x86/memcpy.o
CC bootblock/arch/x86/memset.o
CC bootblock/arch/x86/mmap_boot.o
CC bootblock/arch/x86/walkcbfs.o
CC bootblock/commonlib/cbfs.o
CC bootblock/commonlib/lz4_wrapper.o
CC bootblock/commonlib/mem_pool.o
CC bootblock/commonlib/region.o
CC bootblock/console/die.o
CC bootblock/console/post.o
CC bootblock/cpu/x86/lapic/boot_cpu.o
CC bootblock/cpu/x86/mtrr/earlymtrr.o
CC bootblock/device/device_simple.o
CC bootblock/device/i2c.o
CC bootblock/drivers/uart/uart8250io.o
CC bootblock/drivers/uart/util.o
CC bootblock/lib/boot_device.o
CC bootblock/lib/bootmode.o
FMAP   build/util/cbfstool/fmaptool -h build/fmap_config.h
build/fmap.fmd build/fmap.fmap
SUCCESS: Wrote 182 bytes to file 'build/fmap.fmap' (and generated header)
The sections containing CBFSes are: COREBOOT
CC bootblock/lib/cbfs.o
CC bootblock/lib/cbmem_console.o
CC bootblock/lib/delay.o
CC bootblock/lib/fmap.o
CC bootblock/lib/gcc.o
CC bootblock/lib/halt.o
CC bootblock/lib/hexdump.o
CC bootblock/lib/libgcc.o
CC bootblock/lib/memchr.o
CC bootblock/lib/memcmp.o
CC bootblock/lib/prog_loaders.o
CC bootblock/lib/prog_ops.o
CC bootblock/lib/version.o
CC bootblock/vboot/bootmode.o
LINK   cbfs/fallback/bootblock.debug
OBJCOPYcbfs/fallback/bootblock.elf
OBJCOPYbootblock.raw.bin
CC romstage/mainboard/intel/i946gz/static.o
CC romstage/arch/x86/acpi_s3.o
CC romstage/arch/x86/assembly_entry.o
CC romstage/arch/x86/boot.o
CC romstage/arch/x86/cbfs_and_run.o
CC romstage/arch/x86/cbmem.o
CC romstage/arch/x86/cpu_common.o
CC romstage/arch/x86/memcpy.o
CP romstage/arch/x86/memlayout.ld
CC romstage/arch/x86/memmove.o
CC romstage/arch/x86/memset.o
CC romstage/arch/x86/mmap_boot.o
CC romstage/arch/x86/postcar_loader.o
CC romstage/commonlib/cbfs.o
CC romstage/commonlib/lz4_wrapper.o
CC romstage/commonlib/mem_pool.o
CC romstage/commonlib/region.o
CC romstage/console/console.o
CC romstage/console/die.o
CC romstage/console/init.o
CC romstage/console/post.o
CC romstage/console/printk.o
CC romstage/console/vtxprintf.o
CC romstage/cpu/intel/car/romstage.o
CC romstage/cpu/intel/microcode/microcode.o
CC romstage/cpu/x86/car.o
CC romstage/cpu/x86/lapic/apic_timer.o
CC romstage/cpu/x86/lapic/boot_cpu.o
CC romstage/cpu/x86/mtrr/earlymtrr.o
CC romstage/device/device_simple.o
CC romstage/device/i2c.o
CC romstage/device/pci_early.o
CC romstage/drivers/pc80/rtc/mc146818rtc.o
CC romstage/drivers/pc80/rtc/mc146818rtc_early.o
CC romstage/drivers/uart/uart8250io.o
CC romstage/drivers/uart/util.o
CC romstage/lib/boot_device.o
CC romstage/lib/bootmode.o
CC romstage/lib/cbfs.o
CC romstage/lib/cbmem_common.o
CC romstage/lib/cbmem_console.o
CC romstage/lib/compute_ip_checksum.o
CC romstage/lib/delay.o
CC romstage/lib/fmap.o
CC romstage/lib/gcc.o
CC romstage/lib/halt.o
CC romstage/lib/hexdump.o
CC romstage/lib/imd.o
CC romstage/lib/imd_cbmem.o
CC romstage/lib/libgcc.o
CC romstage/lib/memchr.o
CC romstage/lib/memcmp.o
CC romstage/lib/memrange.o
CC romstage/lib/prog_loaders.o
CC romstage/lib/prog_ops.o
CP romstage/lib/program.ld
CC romstage/lib/ramtest.o
CC romstage/lib/romstage_stack.o
CC romstage/lib/stack.o
CC romstage/lib/version.o
CC romstage/mainboard/intel/i946gz/romstage.o
CC romstage/northbridge/intel/i945/debug.o
CC romstage/northbridge/intel/i945/early_init.o
CC romstage/northbridge/intel/i945/errata.o
CC 

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

[Nico Huber]

On 15.10.2016 15:44, Riko Ho wrote:
> So I must do rm .config and make menu config then don't select :
> 
>  CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM , where is that option, may be I
> did, I forget already...
> Can you read it from .config ?
Yes, it would have shown up as a line that says
CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM=y

> 
> Anyway, what's the safe mode / default for make menuconfig ? What's the
> payload option should I make ?
I usually head straight to the mainboard selection, keeping everything
else as is. The payload doesn't matter, as long as coreboot doesn't boot
through. You can just leave it at the default "SeaBIOS", or change it
to "None" until you have a working coreboot.

Nico

> 
> 
> On 15/10/2016 9:12 PM, Nico Huber wrote
> 
>> On 15.10.2016 14:57, Antonius Riko wrote:
>>> I did rm .config and did make again :
>>>
>>> bianchi@ubuntu:~/coreboot$ make clean
>>> bianchi@ubuntu:~/coreboot$ make
>>> #
>>> # configuration written to /home/bianchi/coreboot/.config
>>> #
>>>  HOSTCC util/sconfig/lex.yy.o
>>>  HOSTCC util/sconfig/sconfig.tab.o
>>>  HOSTCC util/sconfig/main.o
>>>  HOSTCC util/sconfig/sconfig (link)
>>>  SCONFIGmainboard/intel/i946gz/devicetree.cb
>>>  HOSTCC nvramtool/cli/nvramtool.o
>>>  HOSTCC nvramtool/cli/opts.o
>>>  HOSTCC nvramtool/cmos_lowlevel.o
>>>  HOSTCC nvramtool/cmos_ops.o
>>>  HOSTCC nvramtool/common.o
>>>  HOSTCC nvramtool/compute_ip_checksum.o
>>>  HOSTCC nvramtool/hexdump.o
>>>  HOSTCC nvramtool/input_file.o
>>>  HOSTCC nvramtool/layout.o
>>>  HOSTCC nvramtool/accessors/layout-common.o
>>>  HOSTCC nvramtool/accessors/layout-text.o
>>>  HOSTCC nvramtool/accessors/layout-bin.o
>>>  HOSTCC nvramtool/lbtable.o
>>>  HOSTCC nvramtool/reg_expr.o
>>>  HOSTCC nvramtool/cbfs.o
>>>  HOSTCC nvramtool/accessors/cmos-mem.o
>>>  HOSTCC nvramtool/nvramtool (link)
>>>  OPTION option_table.h
>>>  CC bootblock/mainboard/intel/i946gz/static.o
>>>  CC bootblock/arch/x86/boot.o
>>>  GENgenerated/bootblock.ld
>>>  CP bootblock/arch/x86/bootblock.ld
>>>  HOSTCC util/romcc/romcc (this may take a while)
>>>  ROMCC  generated/bootblock.inc
>>>  CC bootblock/arch/x86/bootblock_romcc.o
>>>  CC bootblock/arch/x86/cpu_common.o
>>>  GENbuild.h
>>>  CC bootblock/arch/x86/id.o
>>>  CC bootblock/arch/x86/memcpy.o
>>>  CC bootblock/arch/x86/memset.o
>>>  CC bootblock/arch/x86/mmap_boot.o
>>>  CC bootblock/arch/x86/timestamp.o
>>>  CC bootblock/arch/x86/walkcbfs.o
>>>  CC bootblock/commonlib/cbfs.o
>>>  CC bootblock/commonlib/lz4_wrapper.o
>>>  CC bootblock/commonlib/mem_pool.o
>>>  CC bootblock/commonlib/region.o
>>>  CC bootblock/console/die.o
>>>  CC bootblock/console/post.o
>>>  CC bootblock/cpu/x86/lapic/boot_cpu.o
>>>  CC bootblock/cpu/x86/mtrr/earlymtrr.o
>>>  CC bootblock/device/device_simple.o
>>>  CC bootblock/device/i2c.o
>>>  CC bootblock/drivers/uart/uart8250io.o
>>>  CC bootblock/drivers/uart/util.o
>>>  CC bootblock/lib/boot_device.o
>>>  CC bootblock/lib/bootmode.o
>>>  HOSTCC cbfstool/fmaptool.o
>>>  HOSTCC cbfstool/cbfs_sections.o
>>>  HOSTCC cbfstool/fmap_from_fmd.o
>>>  HOSTCC cbfstool/fmd.o
>>>  HOSTCC cbfstool/fmd_parser.o
>>>  HOSTCC cbfstool/fmd_scanner.o
>>>  HOSTCC cbfstool/fmap.o
>>>  HOSTCC cbfstool/kv_pair.o
>>>  HOSTCC cbfstool/valstr.o
>>>  HOSTCC cbfstool/fmaptool (link)
>>>  FMAP   build/util/cbfstool/fmaptool -h build/fmap_config.h
>>> build/fmap.fmd build/fmap.fmap
>>> SUCCESS: Wrote 182 bytes to file 'build/fmap.fmap' (and generated
>>> header)
>>> The sections containing CBFSes are: COREBOOT
>>>  CC bootblock/lib/cbfs.o
>>>  CC bootblock/lib/cbmem_console.o
>>>  CC bootblock/lib/delay.o
>>>  CC bootblock/lib/fmap.o
>>>  CC bootblock/lib/gcc.o
>>>  CC bootblock/lib/halt.o
>>>  CC bootblock/lib/hexdump.o
>>>  CC bootblock/lib/libgcc.o
>>>  CC bootblock/lib/memchr.o
>>>  CC bootblock/lib/memcmp.o
>>>  CC bootblock/lib/prog_loaders.o
>>>  CC bootblock/lib/prog_ops.o
>>>  CC bootblock/lib/timestamp.o
>>>  CC bootblock/lib/version.o
>>>  CC bootblock/vboot/bootmode.o
>>>  LINK   cbfs/fallback/bootblock.debug
>>>  OBJCOPYcbfs/fallback/bootblock.elf
>>>  OBJCOPYbootblock.raw.bin
>>>  CC romstage/mainboard/intel/i946gz/static.o
>>>  CC 

Re: [coreboot] ARMv8 prototype in simulator failing at payload_load()

[tmiket]

Julius,
I appreciate the background on the API change and the pointer
to what to fix in the code.  I have stubbed out the soc chip operations
and now am letting coreboot know that there is a region of dram.
The simulation train continues.
Cheers,
T.mike

On 2016-10-13 14:30, Julius Werner wrote:

You need a call like ram_resource(, 0, , ); somewhere in ramstage... e.g. as in
src/soc/rockchip/rk3288/soc.c. Even if you're running on an emulator,
you'll still have to decide on a memory range that you want to be your
emulated DRAM so that coreboot knows where it can put stuff.

Can anybody comment on this suspicion, as well as why the check is 
enabled

for payload load but disabled for bl31 load?


This was a recent change that became necessary to support a special
case... before that, the check was always mandatory. The memory
allocator situation is a little ugly on non-x86 devices since they
usually have separate SRAM and DRAM areas. The resource allocator was
written for x86 and only meant to dynamically track DRAM (and
non-memory) resources in ramstage. On non-x86 devices it became
necessary to handle SRAM allocations in earlier stages and we invented
the static memlayout.ld mechanism. The two don't really talk much, and
thus the ramstage resource allocator doesn't know about SRAM (we
should probably try to improve that, but as usual, it's a little
tricky in the details and nobody has the time right now). We needed
BL31 to be loaded through the same mechanism as the payload, but some
platforms want to place (parts of) it in SRAM... so we had to hack out
the usable memory check for it to get it to work. You can see some of
the original discussion in
https://chromium-review.googlesource.com/c/376849/.


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Re: [coreboot] Attempt to porting coreboot to Gigabyte ga-945gcm-s2l

[Arthur Heymans]

Nico Huber  writes:

> Hi Arthur,
>
>
> This is just a synchronization point. The wbinvd() is there to ensure
> that the memcpy() above has reached real RAM before the program con-
> tinues.
>
> As this fails right after resources have been assigned to all devices, I
> suspected a resource conflict but couldn't find any trouble in your log.
>
> Another thing that can cause trouble is the MTRR configuration. I have
> no idea in which state they are / should be in your case, though.

It really is a raminit issue. I tested with a 800MHz fsb (does not even get
to ramstage) and a 533MHz fsb cpu which just works (this is a 1067fsb cpu with
tape on bsel0 pin to make it select 533fsb). So unless 945gc raminit
gets fixed, this port is quite useless.

This i945 raminit.c seems to have a lot of code specific for 667fsb
(laptops only) and 533fsb (Intel d945gclf atom board).

I guess I'll have to run vendor through serialICE and see how MCHBARS are 
configured
with inteltool with 800fsb and 1067fsb cpus.

Kind regards
-- 
Arthur Heymans

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Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

[Riko Ho]

So I must do rm .config and make menu config then don't select :

 CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM , where is that option, may be I did, I 
forget already...
Can you read it from .config ?

Anyway, what's the safe mode / default for make menuconfig ? What's the payload 
option should I make ?


On 15/10/2016 9:12 PM, Nico Huber wrote


On 15.10.2016 14:57, Antonius Riko wrote:

I did rm .config and did make again :

bianchi@ubuntu:~/coreboot$ make clean
bianchi@ubuntu:~/coreboot$ make
#
# configuration written to /home/bianchi/coreboot/.config
#
 HOSTCC util/sconfig/lex.yy.o
 HOSTCC util/sconfig/sconfig.tab.o
 HOSTCC util/sconfig/main.o
 HOSTCC util/sconfig/sconfig (link)
 SCONFIGmainboard/intel/i946gz/devicetree.cb
 HOSTCC nvramtool/cli/nvramtool.o
 HOSTCC nvramtool/cli/opts.o
 HOSTCC nvramtool/cmos_lowlevel.o
 HOSTCC nvramtool/cmos_ops.o
 HOSTCC nvramtool/common.o
 HOSTCC nvramtool/compute_ip_checksum.o
 HOSTCC nvramtool/hexdump.o
 HOSTCC nvramtool/input_file.o
 HOSTCC nvramtool/layout.o
 HOSTCC nvramtool/accessors/layout-common.o
 HOSTCC nvramtool/accessors/layout-text.o
 HOSTCC nvramtool/accessors/layout-bin.o
 HOSTCC nvramtool/lbtable.o
 HOSTCC nvramtool/reg_expr.o
 HOSTCC nvramtool/cbfs.o
 HOSTCC nvramtool/accessors/cmos-mem.o
 HOSTCC nvramtool/nvramtool (link)
 OPTION option_table.h
 CC bootblock/mainboard/intel/i946gz/static.o
 CC bootblock/arch/x86/boot.o
 GENgenerated/bootblock.ld
 CP bootblock/arch/x86/bootblock.ld
 HOSTCC util/romcc/romcc (this may take a while)
 ROMCC  generated/bootblock.inc
 CC bootblock/arch/x86/bootblock_romcc.o
 CC bootblock/arch/x86/cpu_common.o
 GENbuild.h
 CC bootblock/arch/x86/id.o
 CC bootblock/arch/x86/memcpy.o
 CC bootblock/arch/x86/memset.o
 CC bootblock/arch/x86/mmap_boot.o
 CC bootblock/arch/x86/timestamp.o
 CC bootblock/arch/x86/walkcbfs.o
 CC bootblock/commonlib/cbfs.o
 CC bootblock/commonlib/lz4_wrapper.o
 CC bootblock/commonlib/mem_pool.o
 CC bootblock/commonlib/region.o
 CC bootblock/console/die.o
 CC bootblock/console/post.o
 CC bootblock/cpu/x86/lapic/boot_cpu.o
 CC bootblock/cpu/x86/mtrr/earlymtrr.o
 CC bootblock/device/device_simple.o
 CC bootblock/device/i2c.o
 CC bootblock/drivers/uart/uart8250io.o
 CC bootblock/drivers/uart/util.o
 CC bootblock/lib/boot_device.o
 CC bootblock/lib/bootmode.o
 HOSTCC cbfstool/fmaptool.o
 HOSTCC cbfstool/cbfs_sections.o
 HOSTCC cbfstool/fmap_from_fmd.o
 HOSTCC cbfstool/fmd.o
 HOSTCC cbfstool/fmd_parser.o
 HOSTCC cbfstool/fmd_scanner.o
 HOSTCC cbfstool/fmap.o
 HOSTCC cbfstool/kv_pair.o
 HOSTCC cbfstool/valstr.o
 HOSTCC cbfstool/fmaptool (link)
 FMAP   build/util/cbfstool/fmaptool -h build/fmap_config.h
build/fmap.fmd build/fmap.fmap
SUCCESS: Wrote 182 bytes to file 'build/fmap.fmap' (and generated header)
The sections containing CBFSes are: COREBOOT
 CC bootblock/lib/cbfs.o
 CC bootblock/lib/cbmem_console.o
 CC bootblock/lib/delay.o
 CC bootblock/lib/fmap.o
 CC bootblock/lib/gcc.o
 CC bootblock/lib/halt.o
 CC bootblock/lib/hexdump.o
 CC bootblock/lib/libgcc.o
 CC bootblock/lib/memchr.o
 CC bootblock/lib/memcmp.o
 CC bootblock/lib/prog_loaders.o
 CC bootblock/lib/prog_ops.o
 CC bootblock/lib/timestamp.o
 CC bootblock/lib/version.o
 CC bootblock/vboot/bootmode.o
 LINK   cbfs/fallback/bootblock.debug
 OBJCOPYcbfs/fallback/bootblock.elf
 OBJCOPYbootblock.raw.bin
 CC romstage/mainboard/intel/i946gz/static.o
 CC romstage/arch/x86/acpi_s3.o
 GENgenerated/assembly.inc
 CC romstage/arch/x86/assembly_entry.o
 CC romstage/arch/x86/boot.o
 CC romstage/arch/x86/cbfs_and_run.o
 CC romstage/arch/x86/cbmem.o
 CC romstage/arch/x86/cpu_common.o
 CC romstage/arch/x86/memcpy.o
 CP romstage/arch/x86/memlayout.ld
 CC romstage/arch/x86/memmove.o
 CC romstage/arch/x86/memset.o
 CC romstage/arch/x86/mmap_boot.o
 CC romstage/arch/x86/postcar_loader.o
 CC romstage/arch/x86/timestamp.o
 CC romstage/commonlib/cbfs.o
 CC romstage/commonlib/lz4_wrapper.o
 CC romstage/commonlib/mem_pool.o
 CC romstage/commonlib/region.o

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

[Nico Huber]

Hi,

On 15.10.2016 13:26, Antonius Riko wrote:
> I closed the patch
> 
> //#include 
> //#include 
> //#include 
> 
> and I got error :
> 
> bianchi@ubuntu:~/coreboot$ make
> GENgenerated/bootblock.ld
> CP bootblock/arch/x86/bootblock.ld
> LINK   cbfs/fallback/bootblock.debug
> OBJCOPYcbfs/fallback/bootblock.elf
> OBJCOPYbootblock.raw.bin
> CC romstage/mainboard/intel/i946gz/romstage.o
> LINK   cbfs/fallback/romstage.debug
> build/romstage/mainboard/intel/i946gz/romstage.o: In function
> `mainboard_romstage_entry':
> /home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:214:
> undefined reference to `southbridge_detect_s3_resume'
> /home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:217:
> undefined reference to `enable_smbus'
> build/romstage/northbridge/intel/i945/raminit.o: In function `spd_read_byte':
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
> undefined reference to `smbus_read_byte'
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
> undefined reference to `smbus_read_byte'
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
> undefined reference to `smbus_read_byte'
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
> undefined reference to `smbus_read_byte'
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
> undefined reference to `smbus_read_byte'
> build/romstage/northbridge/intel/i945/raminit.o:/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
> more undefined references to `smbus_read_byte' follow
> src/arch/x86/Makefile.inc:264: recipe for target
> 'build/cbfs/fallback/romstage.debug' failed
> make: *** [build/cbfs/fallback/romstage.debug] Error 1

it's hard to reproduce with only the Kconfig snippet. Here's what I've
tried: copied src/mainboard/intel/d945gclf to i946gz, used your Kconfig
below and the following Kconfig.name:

config BOARD_INTEL_I946GZ
bool "I946GZ"

Then I got:
build/romstage/mainboard/intel/i946gz/romstage.o: In function
`mainboard_romstage_entry':
/home/icon/coreboot/src/mainboard/intel/i946gz/romstage.c:162: undefined
reference to `lpc47m15x_enable_serial'
/home/icon/coreboot/src/mainboard/intel/i946gz/romstage.c:163: undefined
reference to `lpc47m15x_enable_serial'

which is ok, given that I mixed the d945gclf/romstage.c with your
Kconfig.

Maybe it's just a leftover from your previous try; did you do a `make
clean`? If that doesn't help, maybe your .config is just messed up
because of the Kconfig changes. You should try with a fresh .config
(i.e. `rm .config` then `make menuconfig` again and select intel/i945gz).

Nico

PS. Please use the "reply" function of your mail client, if it has any.
That way mails can be sorted in one thread correctly which makes
the mailing list life a lot easier.

> 
> my Kconfig at /src/mainboard/intel/i946gz :
> 
> ##
> ## This file is part of the coreboot project.
> ##
> ## Copyright (C) 2009 coresystems GmbH
> ##
> ## This program is free software; you can redistribute it and/or modify
> ## it under the terms of the GNU General Public License as published by
> ## the Free Software Foundation; version 2 of the License.
> ##
> ## This program is distributed in the hope that it will be useful,
> ## but WITHOUT ANY WARRANTY; without even the implied warranty of
> ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> ## GNU General Public License for more details.
> ##
> if BOARD_INTEL_I946GZ
> 
> config BOARD_SPECIFIC_OPTIONS # dummy
>   def_bool y
>   select CPU_INTEL_SOCKET_LGA775
> select NORTHBRIDGE_INTEL_I945
>   select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
>   ##select NORTHBRIDGE_INTEL_I946GZ
>   ##select NORTHBRIDGE_INTEL_SUBTYPE_I946GZ
>   select CHECK_SLFRCS_ON_RESUME
>   select SOUTHBRIDGE_INTEL_I82801GX
>   select SUPERIO_ITE_IT8718F
>   select HAVE_OPTION_TABLE
>   select HAVE_PIRQ_TABLE
>   select HAVE_MP_TABLE
>   select HAVE_ACPI_TABLES
>   select HAVE_ACPI_RESUME
>   select BOARD_ROMSIZE_KB_512
>   select CHANNEL_XOR_RANDOMIZATION
>   select MAINBOARD_HAS_NATIVE_VGA_INIT
>   select INTEL_EDID
> 
> config MAINBOARD_DIR
>   string
>   default intel/i946gz
> 
> config MAINBOARD_PART_NUMBER
>   string
>   default "I946GZ"
> 
> config MMCONF_BASE_ADDRESS
>   hex
>   default 0xf000
> 
> config IRQ_SLOT_COUNT
>   int
>   default 18
> 
> config MAX_CPUS
>   int
>   default 1
> 
> endif # BOARD_INTEL_I946GZ
> 
> 
> 
> Including .c files is a bad idea. We did that before and still do in
> some places, but will get rid of it in the future hopefully. Also you
> are mixing romstage (early_*.c) and ramstage (lpc.c) code here.
> 
> I guess the remaining errors are caused by the mixing.
> 
> Hope that helps,
> Nico
> 
> ==
> 
> 
> 


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Re: [coreboot] Official builds for EoL Chromebooks

[John Lewis]

Yes, I think in this case you're mixing your alternate realities. No, no
direct association.


On 15/10/16 11:44, Zoran Stojsavljevic wrote:
> Hello John,
>
> I'll investigate this in depth... Somehow, I remember, you were
> connected with them (anyhow - as free lancer, or in different way),
> aren't you? ;-)
>
> Maybe I am just too old dummy cat, and I mix virtual realities...
> Everything is possible! I admit.
>
> Thank you,
> Zoran
>
> On 10/15/16, John Lewis  wrote:
>> On 13/10/16 20:45, Zoran Stojsavljevic wrote:
 John Lewis has some upstream firmware for the older
>>> SandyBridge/IvyBridge models,
 but his Haswell firmware is build from Google's tree/branches not
>>> upstream.
 He also has no plans for any future upstream firmware.
>>> Once upon a time when John worked for SAGE Electronics. I remember
>>> this time, about 3 and more years ago. ;-)
>>>
>> I never worked for Sage.
>>> SAGE was the first company (FSP echo system partner) to accept and
>>> adopt INTEL FSP (midst of 2013, IVB was the first child). Since then,
>>> lot of things have changed. Lot of... SAGE is not anymore in this
>>> business, and, and... .. . (you all fill in the dots). :-)
>>>
>>> Zoran
>>>
>>> On Thu, Oct 13, 2016 at 4:53 PM, Matt DeVillier
>>> > wrote:
>>>
>>> Emi,
>>>
>>> I think this is what you're looking
>>> for: https://www.coreboot.org/Supported_Motherboards
>>> 
>>> It contains the commit hash, build config, and a few other logs
>>> for each device/commit.  It is user submitted though, since there
>>> doesn't exist a test setup for every supported device.
>>>
>>> Right now, I'm the main builder/distributor of upstream coreboot
>>> firmware for ChromeOS devices; I support all Haswell, Broadwell,
>>> and some Baytrail devices, the former with both UEFI and Legacy
>>> Boot variants. When time permits, I'll expand that to cover the
>>> rest of the Baytrail devices, then move on to adding support for
>>> Skylake.  No plans for Braswell support unless I acquire a device
>>> on which to test.
>>>
>>> John Lewis has some upstream firmware for the older
>>> SandyBridge/IvyBridge models, but his Haswell firmware is build
>>> from Google's tree/branches not upstream.  He also has no plans
>>> for any future upstream firmware.
>>>
>>> cheers,
>>> Matt
>>>
>>> On Thu, Oct 13, 2016 at 6:49 AM, Emilian Bold
>>> > wrote:
>>>
>>> Hello,
>>>
>>> Now that Coreboot has reproducible builds, could you provide a
>>> list of build hashes for Chromebooks that are or will soon
>>> reach End of Life?
>>>
>>> I see
>>> on https://support.google.com/chrome/a/answer/6220366?hl=en
>>>  that
>>> 2 Chromebooks will reach End of Life in 2016 and 3 more in
>>> 2017 then 7 in 2018. I assume the number will increase each year.
>>>
>>> I know that Coreboot does not distribute builds, but the
>>> little Custom roms section
>>> on https://www.coreboot.org/users.html
>>>  seems insufficient.
>>>
>>> It's easy making a build, you just need to have the certainty
>>> you did it well. Or that the one you are downloading is correct.
>>>
>>> Posting an official SHA-256 hash for a ROM would solve this.
>>>
>>> --emi
>>>
>>> --
>>> coreboot mailing list: coreboot@coreboot.org
>>> 
>>> https://www.coreboot.org/mailman/listinfo/coreboot
>>> 
>>>
>>>
>>>
>>> --
>>> coreboot mailing list: coreboot@coreboot.org
>>> 
>>> https://www.coreboot.org/mailman/listinfo/coreboot
>>> 
>>>
>>>
>>>
>>>
>>


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Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

[Antonius Riko]

Thanks, for the response
Here's what I've got, what else do I miss here ?

I closed the patch

//#include 
//#include 
//#include 

and I got error :
bianchi at ubuntu
:~/coreboot$ make
GENgenerated/bootblock.ld
CP bootblock/arch/x86/bootblock.ld
LINK   cbfs/fallback/bootblock.debug
OBJCOPYcbfs/fallback/bootblock.elf
OBJCOPYbootblock.raw.bin
CC romstage/mainboard/intel/i946gz/romstage.o
LINK   cbfs/fallback/romstage.debug
build/romstage/mainboard/intel/i946gz/romstage.o: In function
`mainboard_romstage_entry':
/home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:214:
undefined reference to `southbridge_detect_s3_resume'
/home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:217:
undefined reference to `enable_smbus'
build/romstage/northbridge/intel/i945/raminit.o: In function `spd_read_byte':
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
undefined reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
undefined reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
undefined reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
undefined reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
undefined reference to `smbus_read_byte'
build/romstage/northbridge/intel/i945/raminit.o:/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
more undefined references to `smbus_read_byte' follow
src/arch/x86/Makefile.inc:264: recipe for target
'build/cbfs/fallback/romstage.debug' failed
make: *** [build/cbfs/fallback/romstage.debug] Error 1

my Kconfig at /src/mainboard/intel/i946gz :

##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
if BOARD_INTEL_I946GZ

config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_INTEL_SOCKET_LGA775
select NORTHBRIDGE_INTEL_I945
select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
##select NORTHBRIDGE_INTEL_I946GZ
##select NORTHBRIDGE_INTEL_SUBTYPE_I946GZ
select CHECK_SLFRCS_ON_RESUME
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_ITE_IT8718F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_512
select CHANNEL_XOR_RANDOMIZATION
select MAINBOARD_HAS_NATIVE_VGA_INIT
select INTEL_EDID

config MAINBOARD_DIR
string
default intel/i946gz

config MAINBOARD_PART_NUMBER
string
default "I946GZ"

config MMCONF_BASE_ADDRESS
hex
default 0xf000

config IRQ_SLOT_COUNT
int
default 18

config MAX_CPUS
int
default 1

endif # BOARD_INTEL_I946GZ



Including .c files is a bad idea. We did that before and still do in
some places, but will get rid of it in the future hopefully. Also you
are mixing romstage (early_*.c) and ramstage (lpc.c) code here.

I guess the remaining errors are caused by the mixing.

Hope that helps,
Nico
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Re: [coreboot] Official builds for EoL Chromebooks

[Zoran Stojsavljevic]

Hello John,

I'll investigate this in depth... Somehow, I remember, you were
connected with them (anyhow - as free lancer, or in different way),
aren't you? ;-)

Maybe I am just too old dummy cat, and I mix virtual realities...
Everything is possible! I admit.

Thank you,
Zoran

On 10/15/16, John Lewis  wrote:
> On 13/10/16 20:45, Zoran Stojsavljevic wrote:
>> > John Lewis has some upstream firmware for the older
>> SandyBridge/IvyBridge models,
>> > but his Haswell firmware is build from Google's tree/branches not
>> upstream.
>> > He also has no plans for any future upstream firmware.
>>
>> Once upon a time when John worked for SAGE Electronics. I remember
>> this time, about 3 and more years ago. ;-)
>>
> I never worked for Sage.
>> SAGE was the first company (FSP echo system partner) to accept and
>> adopt INTEL FSP (midst of 2013, IVB was the first child). Since then,
>> lot of things have changed. Lot of... SAGE is not anymore in this
>> business, and, and... .. . (you all fill in the dots). :-)
>>
>> Zoran
>>
>> On Thu, Oct 13, 2016 at 4:53 PM, Matt DeVillier
>> > wrote:
>>
>> Emi,
>>
>> I think this is what you're looking
>> for: https://www.coreboot.org/Supported_Motherboards
>> 
>> It contains the commit hash, build config, and a few other logs
>> for each device/commit.  It is user submitted though, since there
>> doesn't exist a test setup for every supported device.
>>
>> Right now, I'm the main builder/distributor of upstream coreboot
>> firmware for ChromeOS devices; I support all Haswell, Broadwell,
>> and some Baytrail devices, the former with both UEFI and Legacy
>> Boot variants. When time permits, I'll expand that to cover the
>> rest of the Baytrail devices, then move on to adding support for
>> Skylake.  No plans for Braswell support unless I acquire a device
>> on which to test.
>>
>> John Lewis has some upstream firmware for the older
>> SandyBridge/IvyBridge models, but his Haswell firmware is build
>> from Google's tree/branches not upstream.  He also has no plans
>> for any future upstream firmware.
>>
>> cheers,
>> Matt
>>
>> On Thu, Oct 13, 2016 at 6:49 AM, Emilian Bold
>> > wrote:
>>
>> Hello,
>>
>> Now that Coreboot has reproducible builds, could you provide a
>> list of build hashes for Chromebooks that are or will soon
>> reach End of Life?
>>
>> I see
>> on https://support.google.com/chrome/a/answer/6220366?hl=en
>>  that
>> 2 Chromebooks will reach End of Life in 2016 and 3 more in
>> 2017 then 7 in 2018. I assume the number will increase each year.
>>
>> I know that Coreboot does not distribute builds, but the
>> little Custom roms section
>> on https://www.coreboot.org/users.html
>>  seems insufficient.
>>
>> It's easy making a build, you just need to have the certainty
>> you did it well. Or that the one you are downloading is correct.
>>
>> Posting an official SHA-256 hash for a ROM would solve this.
>>
>> --emi
>>
>> --
>> coreboot mailing list: coreboot@coreboot.org
>> 
>> https://www.coreboot.org/mailman/listinfo/coreboot
>> 
>>
>>
>>
>> --
>> coreboot mailing list: coreboot@coreboot.org
>> 
>> https://www.coreboot.org/mailman/listinfo/coreboot
>> 
>>
>>
>>
>>
>
>

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[coreboot] TALOS secure workstation campaign has launched

[Leah Rowe]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256

Hello everyone,

Here:
https://www.crowdsupply.com/raptor-computing-systems/talos-secure-workst
ation

This is a high-end desktop/workstation, on par with Intel in terms of
performance, and it's going to ship with entirely libre software on
it, including the boot firmware. From the factory, brand new.
Libreboot is going to support it, once it starts shipping (I'll be
working with Timothy Pearson, the engineer behind the TALOS project,
in my capacity as leader of the libreboot project).

Spread the word! This campaign needs to succeed.

- -- 
Leah Rowe

Libreboot developer

Use free software. Free as in freedom.
https://en.wikipedia.org/wiki/Free_software

Use a free operating system, GNU/Linux.
https://libreboot.org/docs/distros/
Or BSD:
https://libreboot.org/docs/bsd/

Use a free BIOS.
https://libreboot.org/

Support computer user freedom.
https://peers.community/

Minifree Ltd, trading as Ministry of Freedom | Registered in England,
No. 9361826 | VAT No. GB202190462
Registered Office: 19 Hilton Road, Canvey Island, Essex SS8 9QA, UK |
Web: http://minifree.org/
-BEGIN PGP SIGNATURE-

iQEcBAEBCAAGBQJYAgPKAAoJEP9Ft0z50c+Uv0UH/iWZt7ZZAMyiFjwv4y7Xa8zM
jENqT3Q86PV0f45pB0262/ABtA1loBTmJ4ag7Y9WB4fg6BlgK0BV4snwoUKazMB7
j9CCzHfAPpkTKjY4t+rTu5fH8Yx2EdinhgjQi0SW8pYYn8bu+XlheLKDvflOcaIc
TXRWhU8D/x77FbKWNePuG9xQCoOIPaQ+JKwrKmk1Q4iepaFhzRh7edoFpVBhnJeV
vMS5myX7oJgTwuLEsh41CT0wc8vmZEW8APcCsYYzmzi6STE5uqzoKoPWw+Jst5Av
agD7X/N0nNjcLnk0q3FTMOolC4Tk1+G7E6eSnukZq3q/RZUmkvZ3YefEZOtnHjs=
=VW6q
-END PGP SIGNATURE-

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Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

[Nico Huber]

Hi Rick,

from your messages on IRC, I guess you almost got it. You have to select
SOUTHBRIDGE_INTEL_I82801GX in your mainboard's Kconfig. Just do a `git
grep select\ SOUTHBRIDGE_INTEL_I82801GX` and you'll find where it's set
for other boards. The correct files should then be added by Makefiles.

More answers inline below...

On 15.10.2016 10:24, Antonius Riko wrote:
> Everyone,
> 
> I tried to port I946GZ and following from 945 example on intel mainboard,
> 
> and I got error when compiling :
> 
> build/romstage/mainboard/intel/i946gz/romstage.o: In function
> `mainboard_romstage_entry':
> /home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:214: undefined
> reference to `southbridge_detect_s3_resume'
> /home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:217: undefined
> reference to `enable_smbus'
> build/romstage/northbridge/intel/i945/raminit.o: In function
> `spd_read_byte':
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
> reference to `smbus_read_byte'
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
> reference to `smbus_read_byte'
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
> reference to `smbus_read_byte'
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
> reference to `smbus_read_byte'
> /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
> reference to `smbus_read_byte'
> build/romstage/northbridge/intel/i945/raminit.o:/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
> more undefined references to `smbus_read_byte' follow
> src/arch/x86/Makefile.inc:264: recipe for target
> 'build/cbfs/fallback/romstage.debug' failed
> make: *** [build/cbfs/fallback/romstage.debug] Error 1
> 
> When I patch it with :
> 
> #include 
> #include 
> #include 

Including .c files is a bad idea. We did that before and still do in
some places, but will get rid of it in the future hopefully. Also you
are mixing romstage (early_*.c) and ramstage (lpc.c) code here.

I guess the remaining errors are caused by the mixing.

Hope that helps,
Nico

> 
> the errors are gone but I got :
>GENgenerated/bootblock.ld
> CP bootblock/arch/x86/bootblock.ld
> LINK   cbfs/fallback/bootblock.debug
> OBJCOPYcbfs/fallback/bootblock.elf
> OBJCOPYbootblock.raw.bin
> CC romstage/mainboard/intel/i946gz/romstage.o
> In file included from src/mainboard/intel/i946gz/romstage.c:44:0:
> src/southbridge/intel/i82801gx/lpc.c: In function 'i82801gx_enable_ioapic':
> src/southbridge/intel/i82801gx/lpc.c:52:20: error: passing argument 1 of
> 'pcie_write_config8' makes integer from pointer without a cast
> [-Werror=int-conversion]
>   pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
> ^
> In file included from src/arch/x86/include/arch/io.h:247:0,
>  from src/mainboard/intel/i946gz/romstage.c:20:
> src/arch/x86/include/arch/pci_mmio_cfg.h:49:6: note: expected 'pci_devfn_t
> {aka unsigned int}' but argument is of type 'struct device *'
>  void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value)
>   ^
> In file included from src/mainboard/intel/i946gz/romstage.c:44:0:
> src/southbridge/intel/i82801gx/lpc.c: In function
> 'i82801gx_enable_serial_irqs':
> src/southbridge/intel/i82801gx/lpc.c:66:20: error: passing argument 1 of
> 'pcie_write_config8' makes integer from pointer without a cast
> [-Werror=int-conversion]
>   pci_write_config8(dev, SERIRQ_CNTL,
> ^
> In file included from src/arch/x86/include/arch/io.h:247:0,
>  from src/mainboard/intel/i946gz/romstage.c:20:
> src/arch/x86/include/arch/pci_mmio_cfg.h:49:6: note: expected 'pci_devfn_t
> {aka unsigned int}' but argument is of type 'struct device *'
>  void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value)
>   ^
> In file included from src/mainboard/intel/i946gz/romstage.c:44:0:
> src/southbridge/intel/i82801gx/lpc.c: In function 'i82801gx_pirq_init':
> src/southbridge/intel/i82801gx/lpc.c:95:24: error: invalid type argument of
> '->' (have 'device_t {aka unsigned int}')
>   config_t *config = dev->chip_info;
> ^
> src/southbridge/intel/i82801gx/lpc.c:97:43: error: dereferencing pointer to
> incomplete type 'config_t {aka struct southbridge_intel_i82801gx_config}'
>   pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
>^
> src/southbridge/intel/i82801gx/lpc.c:111:17: error: 'all_devices'
> undeclared (first use in this function)
>   for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
>  ^
> src/southbridge/intel/i82801gx/lpc.c:111:17: note: each undeclared
> identifier is reported only once for each function it appears in
> src/southbridge/intel/i82801gx/lpc.c:111:56: error: invalid type argument
> of '->' (have 'device_t {aka unsigned int}')
>   for (irq_dev = 

Re: [coreboot] Official builds for EoL Chromebooks

[John Lewis]

On 13/10/16 20:45, Zoran Stojsavljevic wrote:
> > John Lewis has some upstream firmware for the older
> SandyBridge/IvyBridge models,
> > but his Haswell firmware is build from Google's tree/branches not
> upstream.
> > He also has no plans for any future upstream firmware.
>
> Once upon a time when John worked for SAGE Electronics. I remember
> this time, about 3 and more years ago. ;-)
>
I never worked for Sage.
> SAGE was the first company (FSP echo system partner) to accept and
> adopt INTEL FSP (midst of 2013, IVB was the first child). Since then,
> lot of things have changed. Lot of... SAGE is not anymore in this
> business, and, and... .. . (you all fill in the dots). :-)
>
> Zoran
>
> On Thu, Oct 13, 2016 at 4:53 PM, Matt DeVillier
> > wrote:
>
> Emi,
>
> I think this is what you're looking
> for: https://www.coreboot.org/Supported_Motherboards
> 
> It contains the commit hash, build config, and a few other logs
> for each device/commit.  It is user submitted though, since there
> doesn't exist a test setup for every supported device.
>
> Right now, I'm the main builder/distributor of upstream coreboot
> firmware for ChromeOS devices; I support all Haswell, Broadwell,
> and some Baytrail devices, the former with both UEFI and Legacy
> Boot variants. When time permits, I'll expand that to cover the
> rest of the Baytrail devices, then move on to adding support for
> Skylake.  No plans for Braswell support unless I acquire a device
> on which to test.
>
> John Lewis has some upstream firmware for the older
> SandyBridge/IvyBridge models, but his Haswell firmware is build
> from Google's tree/branches not upstream.  He also has no plans
> for any future upstream firmware.
>
> cheers,
> Matt
>
> On Thu, Oct 13, 2016 at 6:49 AM, Emilian Bold
> > wrote:
>
> Hello,
>
> Now that Coreboot has reproducible builds, could you provide a
> list of build hashes for Chromebooks that are or will soon
> reach End of Life?
>
> I see
> on https://support.google.com/chrome/a/answer/6220366?hl=en
>  that
> 2 Chromebooks will reach End of Life in 2016 and 3 more in
> 2017 then 7 in 2018. I assume the number will increase each year.
>
> I know that Coreboot does not distribute builds, but the
> little Custom roms section
> on https://www.coreboot.org/users.html
>  seems insufficient.
>
> It's easy making a build, you just need to have the certainty
> you did it well. Or that the one you are downloading is correct.
>
> Posting an official SHA-256 hash for a ROM would solve this.
>
> --emi
>
> --
> coreboot mailing list: coreboot@coreboot.org
> 
> https://www.coreboot.org/mailman/listinfo/coreboot
> 
>
>
>
> --
> coreboot mailing list: coreboot@coreboot.org
> 
> https://www.coreboot.org/mailman/listinfo/coreboot
> 
>
>
>
>

-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] southbridge/intel/i82801gx/i82801gx.h

[Antonius Riko]

Everyone,

I tried to port I946GZ and following from 945 example on intel mainboard,

and I got error when compiling :

build/romstage/mainboard/intel/i946gz/romstage.o: In function
`mainboard_romstage_entry':
/home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:214: undefined
reference to `southbridge_detect_s3_resume'
/home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:217: undefined
reference to `enable_smbus'
build/romstage/northbridge/intel/i945/raminit.o: In function
`spd_read_byte':
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
reference to `smbus_read_byte'
/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined
reference to `smbus_read_byte'
build/romstage/northbridge/intel/i945/raminit.o:/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62:
more undefined references to `smbus_read_byte' follow
src/arch/x86/Makefile.inc:264: recipe for target
'build/cbfs/fallback/romstage.debug' failed
make: *** [build/cbfs/fallback/romstage.debug] Error 1

When I patch it with :

#include 
#include 
#include 

the errors are gone but I got :
   GENgenerated/bootblock.ld
CP bootblock/arch/x86/bootblock.ld
LINK   cbfs/fallback/bootblock.debug
OBJCOPYcbfs/fallback/bootblock.elf
OBJCOPYbootblock.raw.bin
CC romstage/mainboard/intel/i946gz/romstage.o
In file included from src/mainboard/intel/i946gz/romstage.c:44:0:
src/southbridge/intel/i82801gx/lpc.c: In function 'i82801gx_enable_ioapic':
src/southbridge/intel/i82801gx/lpc.c:52:20: error: passing argument 1 of
'pcie_write_config8' makes integer from pointer without a cast
[-Werror=int-conversion]
  pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
^
In file included from src/arch/x86/include/arch/io.h:247:0,
 from src/mainboard/intel/i946gz/romstage.c:20:
src/arch/x86/include/arch/pci_mmio_cfg.h:49:6: note: expected 'pci_devfn_t
{aka unsigned int}' but argument is of type 'struct device *'
 void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value)
  ^
In file included from src/mainboard/intel/i946gz/romstage.c:44:0:
src/southbridge/intel/i82801gx/lpc.c: In function
'i82801gx_enable_serial_irqs':
src/southbridge/intel/i82801gx/lpc.c:66:20: error: passing argument 1 of
'pcie_write_config8' makes integer from pointer without a cast
[-Werror=int-conversion]
  pci_write_config8(dev, SERIRQ_CNTL,
^
In file included from src/arch/x86/include/arch/io.h:247:0,
 from src/mainboard/intel/i946gz/romstage.c:20:
src/arch/x86/include/arch/pci_mmio_cfg.h:49:6: note: expected 'pci_devfn_t
{aka unsigned int}' but argument is of type 'struct device *'
 void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value)
  ^
In file included from src/mainboard/intel/i946gz/romstage.c:44:0:
src/southbridge/intel/i82801gx/lpc.c: In function 'i82801gx_pirq_init':
src/southbridge/intel/i82801gx/lpc.c:95:24: error: invalid type argument of
'->' (have 'device_t {aka unsigned int}')
  config_t *config = dev->chip_info;
^
src/southbridge/intel/i82801gx/lpc.c:97:43: error: dereferencing pointer to
incomplete type 'config_t {aka struct southbridge_intel_i82801gx_config}'
  pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
   ^
src/southbridge/intel/i82801gx/lpc.c:111:17: error: 'all_devices'
undeclared (first use in this function)
  for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 ^
src/southbridge/intel/i82801gx/lpc.c:111:17: note: each undeclared
identifier is reported only once for each function it appears in
src/southbridge/intel/i82801gx/lpc.c:111:56: error: invalid type argument
of '->' (have 'device_t {aka unsigned int}')
  for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
^
src/southbridge/intel/i82801gx/lpc.c:114:15: error: invalid type argument
of '->' (have 'device_t {aka unsigned int}')
   if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
   ^
src/southbridge/intel/i82801gx/lpc.c:114:35: error: invalid type argument
of '->' (have 'device_t {aka unsigned int}')
   if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
   ^
src/southbridge/intel/i82801gx/lpc.c: In function 'i82801gx_gpi_routing':
src/southbridge/intel/i82801gx/lpc.c:136:24: error: invalid type argument
of '->' (have 'device_t {aka unsigned int}')
  config_t *config = dev->chip_info;
^
src/southbridge/intel/i82801gx/lpc.c: In function