Re: [coreboot] C++

I completely agree with Ron (Ron, don't say that I in some cases do not agree with you ;-] ). My ad-hoc very rough estimations will be that you'll shrink around 30/40% of code, but introducing two (virtual) levels of abstraction with (about) three levels of inheritance for real classes will slow

Re: [coreboot] 8 GB DIMMs on Nehalem (Arrandale)

> Both CPUs have PAE support, yes, but I think I have never even tried to > boot a 32-bit kernel on them :) This is one missing info. Because, so far, if you did not know, there are two types of 32-bit kernels: normal 32 bit, and PAE 32 bit. But, in contrary, x86_64 has only one type of kernel

[coreboot] European coreboot conference 2017

Hello everyone, we are currently planning to host a coreboot conference in Germany with 2 days of talks and an additional 2 days of hacking. The date will probably either be October 19-22 or October 26-29, i.e. directly before or after Embedded Linux Conference Europe and LinuxCon Europe.

Re: [coreboot] Does the 62xx Series Opteron work *securely* without microcode?

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 01/28/2017 02:25 PM, Igor Skochinsky wrote: > Hello Timothy, > > Wednesday, January 25, 2017, 6:32:29 PM, you wrote: > > > TP> -BEGIN PGP SIGNED MESSAGE- > TP> Hash: SHA1 > > TP> On 01/25/2017 11:26 AM, Aaron Durbin wrote: >>> On Wed,

Re: [coreboot] Does the 62xx Series Opteron work *securely* without microcode?

Hello Timothy, Wednesday, January 25, 2017, 6:32:29 PM, you wrote: TP> -BEGIN PGP SIGNED MESSAGE- TP> Hash: SHA1 TP> On 01/25/2017 11:26 AM, Aaron Durbin wrote: >> On Wed, Jan 25, 2017 at 11:24 AM, Timothy Pearson >> wrote: >> On 01/24/2017 10:55 PM,

Re: [coreboot] 8 GB DIMMs on Nehalem (Arrandale)

> Not sure if I interpret "within an entire family" correctly, but the > online specs for the 820QM are clearly wrong Yes, this statement is very blurry - I thought about artificial memory limitations like ones in C2000 Atom server series - there are almost identical models (C2530 and C2550 for

Re: [coreboot] C++

On Sat, Jan 28, 2017 at 6:14 AM Philipp Stanner wrote: > Could coreboot (or parts of it) be written in C++? > I hope not. > > What would be the advantages and disadvantages? > > I can't think of a single one, and I see a lot of C++. Note that there are parts of coreboot

Re: [coreboot] 8 GB DIMMs on Nehalem (Arrandale)

On Sat, 28 Jan 2017 17:01:05 +0100 Zoran Stojsavljevic wrote: > Hello Stefan, > > Let me ask you for some other stuff, since I would like to put what I wrote > initially to hold (sleep state, for now). > > You wrote: *The official specs are not trustworthy IMHO

Re: [coreboot] 8 GB DIMMs on Nehalem (Arrandale)

On Sat, 28 Jan 2017 17:01:09 +0300 Andrey Korolyov wrote: > > The chipset in the (QC version of the) W510 is actually exactly the same as > > in the X201 and T410s: Ibex Peak. > > > > But CPUs we are looking at *are* actually different Of course - I did not bring up chipsets

Re: [coreboot] 8 GB DIMMs on Nehalem (Arrandale)

Hello Stefan, Let me ask you for some other stuff, since I would like to put what I wrote initially to hold (sleep state, for now). You wrote: *The official specs are not trustworthy IMHO and cpuid(1) and /proc/cpuinfo **show the same physical address width of 36 bits (which would indicate a

[coreboot] C++

Could coreboot (or parts of it) be written in C++? What would be the advantages and disadvantages? -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] 8 GB DIMMs on Nehalem (Arrandale)

On Sun, 22 Jan 2017 12:33:08 +0100 Zoran Stojsavljevic wrote: > Hello Stefan, > > In addition what Charlotte wrote to you, I would advise you the following > (as general approach for mem problems): > [1] Please, for testing the memory, use secondary Coreboot

Re: [coreboot] 8 GB DIMMs on Nehalem (Arrandale)

> The chipset in the (QC version of the) W510 is actually exactly the same as > in the X201 and T410s: Ibex Peak. > But CPUs we are looking at *are* actually different - scale-down could mean an exposure of a previously unaccounted design issue which actually prevented 32nm CPU 'upgrade' to work

Re: [coreboot] Proposal for new "Commenting" wiki text (was: [RFC] Deciding on style for multi-line comments)

Hi folks, sorry to revive this old, stale topic. I got stalled by a request to ensure the comment style with a script. Now, that I had a look at checkpatch.pl, I don't think this could be done easily without risking many false positives. So I'm again asking to commit my proposal below. I've

Re: [coreboot] 8 GB DIMMs on Nehalem (Arrandale)

On Sat, 21 Jan 2017 18:46:00 -0500 Charlotte Plusplus wrote: > Addressing over 8G is not supported by the chipset used on nehalem thinkpad > laptops (X201) > > Stupid limitation, but it is not the CPU fault. Please don't spread FUD if you don't know what you are