Re: [coreboot] Improving KBC1126 support for HP laptops

[Iru Cai]

On Fri, Feb 24, 2017 at 8:14 AM, Peter Stuge  wrote:

> Iru Cai wrote:
> > I have searched and downloaded two SMSC confidential document: a KBC1122
> > preliminary datasheet and a KBC1122 BIOS porting guide. Is there any
> > problem if I use them to write some code?
>
> Obviously they are copyrighted works, so you can't contribute any
> code which you may have copied from them.
>
>
I see. I just found out that some initialization code from these documents
is just some PNP device init code from pnp_device.c,
and some is already documented in superio/smsc/kbc1100/kbc1100.h, so
currently I don't need these documents. I'm going to use
the DSDT dump to implement other features.

Iru


>
> //Peter
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://www.coreboot.org/mailman/listinfo/coreboot
>



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Re: [coreboot] Coreboot on Thinkpad "X62" (i7-5600u)?

[Peter Stuge]

Rafael Send wrote:
> an old Thinkpad X61 with a custom motherboard in it.

Who made the new mainboard? You should ideally get their cooperation
for your project.


//Peter

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Re: [coreboot] QA: Properly relay results of `checkpatch.pl` check

[Martin Roth]

Hi Paul,
  checkpatch is currently not a gating item in jenkins and should always
pass right now.  The checkpatch build was added to jenkins to allow people
to see at the results of the console output for the patch without having to
download and run checkpatch themselves.

Unfortunately, checkpatch is a lot stricter than we want to be.  It would
require someone who fixes a misspelling on a line to also fix any other
mistakes on that line.  Because of this, we don't want to fail the patch
based on checkpatch errors styleguide issues.  We had discussed adding a
non-failing 'lint' flag to gerrit to notify people that checkpatch was
failing so that they could go look at it, but due to people's workloads,
this hasn't happened yet.  Honestly, it's probably fallen off the radar.

Personally, I still think it's a bad idea to refuse patches that don't pass
checkpatch, but I'd be glad to discuss it.

Also, the error you mentioned WAS noticed, and fixed in a follow-on patch
so that it could be pulled back into the chromium tree.

Martin

On Thu, Feb 23, 2017 at 2:16 PM, Paul Menzel via coreboot <
coreboot@coreboot.org> wrote:

> Dear coreboot folks,
>
>
> Each commit pushed to Gerrit is automatically tested for “formal”
> issues by using `checkpatch.pl`. See for example [1].
>
> Though despite missing a space violating our coding style, which is
> also found by `checkpatch.pl` [2], the comment contains, that no errors
> is found.
>
> > https://qa.coreboot.org/job/coreboot-checkpatch/5142/ : SUCCESS
>
> ```
> ERROR: space required before the open brace '{'
> #49: FILE: src/mainboard/google/gru/pwm_regulator.c:61:
> +   } else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() >=
> 6){
>
> total: 1 errors, 0 warnings, 49 lines checked
> ```
>
> Is there a reason for not relaying these errors?
>
> If not, it’d be great to do so (and for the Chromium and Intel folks to
> also do that in their repository).
>
>
> Thanks,
>
> Paul
>
>
> [1] https://review.coreboot.org/18460
> [2] https://qa.coreboot.org/job/coreboot-checkpatch/5142/console
> --
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> https://www.coreboot.org/mailman/listinfo/coreboot
>
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Re: [coreboot] Improving KBC1126 support for HP laptops

[Peter Stuge]

Iru Cai wrote:
> I have searched and downloaded two SMSC confidential document: a KBC1122
> preliminary datasheet and a KBC1122 BIOS porting guide. Is there any
> problem if I use them to write some code?

Obviously they are copyrighted works, so you can't contribute any
code which you may have copied from them.


//Peter

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Re: [coreboot] Coreboot on Thinkpad "X62" (i7-5600u)?

[Rafael Send]

"MEI device not found". I take it that's good news?

Rafael

On Thu, Feb 23, 2017 at 4:51 AM, Iru Cai  wrote:

> Hello,
>
> On Thu, Feb 23, 2017 at 3:46 PM, Rafael Send  wrote:
>
>> Hello there-
>> I'm assuming this is the right way to ask a general question, but please
>> let me know if it isn't.
>>
>> I have an "X62" laptop, which is actually an old Thinkpad X61 with a
>> custom motherboard in it.
>> This board has an i7-5600u CPU on it, and I was wondering if it was
>> possible to build a version of coreboot for this machine.
>> I see an existing mailing list entry in the archive discussing a
>> Chromebook Pixel with the same CPU, so I'm thinking it may be possible
>> unless I'm missing something major.
>> Since this is a custom motherboard, how would I find out about the Intel
>> Boot Guard and related issues so that I can provide the details for the
>> good folks here?
>>
>
> You can try https://review.coreboot.org/#/c/16328/, or modify some
> instructions in the firmware to see if it still boots.
>
> If boot guard is not enabled, I think booting with coreboot is not so
> hard, but it may be hard to make the EC interface work fine.
>
> Iru
>
> I'm pretty comfortable around Linux but probably would have trouble
>> building this from scratch.
>> Thanks in advance!
>>
>> Rafael
>>
>> --
>> coreboot mailing list: coreboot@coreboot.org
>> https://www.coreboot.org/mailman/listinfo/coreboot
>>
>
>
>
> --
> Please do not send me Microsoft Office/Apple iWork documents. Send
> OpenDocument instead! http://fsf.org/campaigns/opendocument/
>
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[coreboot] QA: Properly relay results of `checkpatch.pl` check

[Paul Menzel via coreboot]

Dear coreboot folks,


Each commit pushed to Gerrit is automatically tested for “formal”
issues by using `checkpatch.pl`. See for example [1].

Though despite missing a space violating our coding style, which is
also found by `checkpatch.pl` [2], the comment contains, that no errors
is found.

> https://qa.coreboot.org/job/coreboot-checkpatch/5142/ : SUCCESS

```
ERROR: space required before the open brace '{'
#49: FILE: src/mainboard/google/gru/pwm_regulator.c:61:
+   } else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() >= 6){

total: 1 errors, 0 warnings, 49 lines checked
```

Is there a reason for not relaying these errors?

If not, it’d be great to do so (and for the Chromium and Intel folks to
also do that in their repository).


Thanks,

Paul


[1] https://review.coreboot.org/18460
[2] https://qa.coreboot.org/job/coreboot-checkpatch/5142/console

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Re: [coreboot] The fastest possible intel free-as-in-freedom pattform not supported now?

[Martin Roth]

I believe that the only Xeon chips that are supported by coreboot are using
the FSP.  These are the Broadwell-DE (Xeon D family) & Ivy Bridge Gladden
(E3-1125C / E3-1105C v2).

Not that they're high power, but the C2000 (Rangeley/Avaton) chips also use
the FSP, but don't have an ME.  These are also the chips that are
reportedly failing now:
http://www.cisco.com/c/en/us/support/web/clock-signal.html#~field

So while I'd love to see it happen, and not to discourage anyone, we'd have
to do some serious work to get the Xeon chips you mentioned running.

Martin

On Wed, Feb 22, 2017 at 6:37 PM,  wrote:

> As we know, since Intel have changed from ICH to PCH we can not fully
> disable ME any more (at the moment, lets see how far leah gets with the
> x220).
>
> After checking the different platforms i find out, that the Intel LGA 1366
> platform can be used!
> This platform still use ICH and not PCH.
>
> https://en.wikipedia.org/wiki/LGA_1366
> https://en.wikipedia.org/wiki/Intel_X58
>
> Later platforms (LGA 2011, LGA 1356, LGA 1155, ...) are PCH based.
>
> The LGA 1366 (Intel X58) supports great six-core CPUs with 32nm like for
> example the Core i7-990X (6x 3,47ghz, 12MB L3 cache). Also Xeon X5690 would
> be great (probably same CPU like the i7-990X.
>
>
> An other probably FLOSS-possible and even faster platform could be the LGA
> 1567. This is some kind of a rare platform based on the the LGA 1366 but is
> been redesigned to support brutally fast CPUs like for example the 10 core
> (20 threads) Xeon E7-2870 / E7-4870 / E7-8870 CPUs.
> https://en.wikipedia.org/wiki/Westmere_%28microarchitecture%29
> https://en.wikipedia.org/wiki/LGA_1567
>
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> https://www.coreboot.org/mailman/listinfo/coreboot
>
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Re: [coreboot] [VERY IMPORTANT] Announcement regarding Apollo Lake Coreboot building

[Zoran Stojsavljevic]

You see, Youness,

The documentation is very scarse, and scares people out of this... If you
would like to bring lot of people, it should be well documented, and the
path well set.

When I do/help some Linux users out of Fedora forum, there I am as blast...
Since most of the stuff is well documented, well explained, and millions of
people use it, so you can find tons of explanation over the www. (and I do
it for years). Here, every here and while everything changes, and there are
handful of people using Coreboot.

Not formula for success, does it? ;-)

Good Luck to you as well,
Zoran

On Thu, Feb 23, 2017 at 5:49 PM, Youness Alaoui <
kakar...@kakaroto.homelinux.net> wrote:

> Zoran,
>
> The blog post is not meant to be documentation, it's just a progress
> report and a *blog post* about the experience and I'm sure it's much less
> confusing than your emails have been so far.
> in menuconfig, in the Chipset section, there's "Add Intel descriptor.bin
> file" (which is what you had enabled, causing the build to fail) and under
> it, there is "Path and filename of the descriptor.bin file", you set it
> there.
> You'll also probably need to extract and include the ME region as well,
> and clone the blobs repository for the microcode updates to be generated
> from tree.
> Apart from that, I suggest you be careful with what you're doing to avoid
> bricking your device, learn what you can about the process, read
> documentation and even read the code if you need to. Randomly thinking that
> there's a "very important announcement" because you didn't understand how
> to compile coreboot (and then refusing to give your config and telling
> developers to look into this 'bug' without giving any more information) is
> not really the way to incite people to help you.
>
> Good luck
> Youness.
>
> On Thu, Feb 23, 2017 at 10:29 AM, Zoran Stojsavljevic <
> zoran.stojsavlje...@gmail.com> wrote:
>
>> Hello Youness (and others),
>>
>> Here, I need to apologize to all Coreboot recipients. Since it was a
>> while, I did peak into that. But... It is NOT You(ness). You got my
>> attention, and, since you blog is very confusing (lack of  some systematic
>> knowledge) about INTEL BSP Technology.
>>
>> I really admire your effort. And just because of that I (after some 6+
>> hours of investigation) I'll try to strengthen out your logs, which are, I
>> should say, puzzled, scrambled all over place. Pieces of Truth are there,
>> and you got on the right path. Although... Labyrinth (unsorted kludges and
>> facts) for most of folks.
>>
>> *I did NOT expect that ... will make out of this Rocket Science.* And
>> yes, they did make it??? Why, that is the question? ;-)
>>
>> I got it. Not quite up to ground level (I need to understand more about
>> make menuconfig setup). But in order to make (example) 8MB Coreboot, you
>> need to take the TRUE APL-I BIOS and to apply IFD tool, in order to extract
>> first 4K (4096) File Descriptor. And SBIOS part as well. Not sure how many
>> parts should be extracted?!
>>
>> Here is what GOOGLE designers posted for Emerald Lake 2, in 3rdparty:
>>
>> [user@localhost emeraldlake2]$ ls -al
>> total 2120
>> drwxrwxr-x. 2 user user4096 Feb 18 01:57 .
>> drwxrwxr-x. 3 user user4096 Feb 18 01:57 ..
>> -rw-rw-r--. 1 user user   4096 Feb 18 01:57 descriptor.bin
>> -rw-rw-r--. 1 user user   2093056 Feb 18 01:57 me.bin
>> -rw-rw-r--. 1 user user   65536 Feb 18 01:57 snm_2120.dat
>> [user@localhost emeraldlake2]$ pwd
>> /home/intel/projects/coreboot/coreboot/3rdparty/blobs/mainbo
>> ard/intel/emeraldlake2
>> [user@localhost emeraldlake2]$
>>
>> And, for descriptor.bin, there is the following:
>>
>> [image: Inline image 1]
>>
>> This (location 0x0010) I have checked with many BIOSes found on the
>> open net, . Most, but I did not find any instance of Apollo Lake, to build
>> proper Coreboot.com.
>>
>> So, I need to extract at least SBIOS and descriptor.bin from real (UEFI)
>> BIOS, and put, where?
>>
>> And then, to add to the Coreboot image. Using make menuconfig. Where and
>> how?
>>
>> (Courtesy Aaron Durbin): http://elinux.org/Min
>> nowboard:MinnowMaxCoreboot#TXE_and_SPI_descriptor
>>
>> Thank you all,
>> Zoran
>>
>> On Thu, Feb 23, 2017 at 12:30 AM, Youness Alaoui <
>> kakar...@kakaroto.homelinux.net> wrote:
>>
>>> Zoran, read this : https://puri.sm/posts/librem
>>> -13-coreboot-report-january-12-2017/
>>> It might help you understand what that IFD and 0x5aa5f00f is (little
>>> endian makes it 0x0FF0A55A)
>>> I had the same confusion when I started, and when I figured things out,
>>> I wrote that blog post that explained the process.
>>>
>>>
>>> On Wed, Feb 22, 2017 at 11:51 AM, Zoran Stojsavljevic <
>>> zoran.stojsavlje...@gmail.com> wrote:
>>>
 So, the final word here: In building of INTEL skus' Coreboot INTEL FIT
 tool (under NDA) is A MUST/mandatory, and INTEL is the road block if you
 are not working with them (having the NDA signed with them)?

 What about the concept of 

Re: [coreboot] [VERY IMPORTANT] Announcement regarding Apollo Lake Coreboot building

[Youness Alaoui]

Zoran,

The blog post is not meant to be documentation, it's just a progress report
and a *blog post* about the experience and I'm sure it's much less
confusing than your emails have been so far.
in menuconfig, in the Chipset section, there's "Add Intel descriptor.bin
file" (which is what you had enabled, causing the build to fail) and under
it, there is "Path and filename of the descriptor.bin file", you set it
there.
You'll also probably need to extract and include the ME region as well, and
clone the blobs repository for the microcode updates to be generated from
tree.
Apart from that, I suggest you be careful with what you're doing to avoid
bricking your device, learn what you can about the process, read
documentation and even read the code if you need to. Randomly thinking that
there's a "very important announcement" because you didn't understand how
to compile coreboot (and then refusing to give your config and telling
developers to look into this 'bug' without giving any more information) is
not really the way to incite people to help you.

Good luck
Youness.

On Thu, Feb 23, 2017 at 10:29 AM, Zoran Stojsavljevic <
zoran.stojsavlje...@gmail.com> wrote:

> Hello Youness (and others),
>
> Here, I need to apologize to all Coreboot recipients. Since it was a
> while, I did peak into that. But... It is NOT You(ness). You got my
> attention, and, since you blog is very confusing (lack of  some systematic
> knowledge) about INTEL BSP Technology.
>
> I really admire your effort. And just because of that I (after some 6+
> hours of investigation) I'll try to strengthen out your logs, which are, I
> should say, puzzled, scrambled all over place. Pieces of Truth are there,
> and you got on the right path. Although... Labyrinth (unsorted kludges and
> facts) for most of folks.
>
> *I did NOT expect that ... will make out of this Rocket Science.* And
> yes, they did make it??? Why, that is the question? ;-)
>
> I got it. Not quite up to ground level (I need to understand more about
> make menuconfig setup). But in order to make (example) 8MB Coreboot, you
> need to take the TRUE APL-I BIOS and to apply IFD tool, in order to extract
> first 4K (4096) File Descriptor. And SBIOS part as well. Not sure how many
> parts should be extracted?!
>
> Here is what GOOGLE designers posted for Emerald Lake 2, in 3rdparty:
>
> [user@localhost emeraldlake2]$ ls -al
> total 2120
> drwxrwxr-x. 2 user user4096 Feb 18 01:57 .
> drwxrwxr-x. 3 user user4096 Feb 18 01:57 ..
> -rw-rw-r--. 1 user user   4096 Feb 18 01:57 descriptor.bin
> -rw-rw-r--. 1 user user   2093056 Feb 18 01:57 me.bin
> -rw-rw-r--. 1 user user   65536 Feb 18 01:57 snm_2120.dat
> [user@localhost emeraldlake2]$ pwd
> /home/intel/projects/coreboot/coreboot/3rdparty/blobs/mainbo
> ard/intel/emeraldlake2
> [user@localhost emeraldlake2]$
>
> And, for descriptor.bin, there is the following:
>
> [image: Inline image 1]
>
> This (location 0x0010) I have checked with many BIOSes found on the
> open net, . Most, but I did not find any instance of Apollo Lake, to build
> proper Coreboot.com.
>
> So, I need to extract at least SBIOS and descriptor.bin from real (UEFI)
> BIOS, and put, where?
>
> And then, to add to the Coreboot image. Using make menuconfig. Where and
> how?
>
> (Courtesy Aaron Durbin): http://elinux.org/Minnowboard:MinnowMaxCoreboot#
> TXE_and_SPI_descriptor
>
> Thank you all,
> Zoran
>
> On Thu, Feb 23, 2017 at 12:30 AM, Youness Alaoui <
> kakar...@kakaroto.homelinux.net> wrote:
>
>> Zoran, read this : https://puri.sm/posts/librem
>> -13-coreboot-report-january-12-2017/
>> It might help you understand what that IFD and 0x5aa5f00f is (little
>> endian makes it 0x0FF0A55A)
>> I had the same confusion when I started, and when I figured things out, I
>> wrote that blog post that explained the process.
>>
>>
>> On Wed, Feb 22, 2017 at 11:51 AM, Zoran Stojsavljevic <
>> zoran.stojsavlje...@gmail.com> wrote:
>>
>>> So, the final word here: In building of INTEL skus' Coreboot INTEL FIT
>>> tool (under NDA) is A MUST/mandatory, and INTEL is the road block if you
>>> are not working with them (having the NDA signed with them)?
>>>
>>> What about the concept of an Open Source??? ;-)
>>>
>>> I am at this point very confused... Really, I am. I did NOT find
>>> anywhere in any document that for Coreboot building INTEL FIT is
>>> mandatory???
>>>
>>> Thank you,
>>> Zoran
>>>
>>> On Wed, Feb 22, 2017 at 5:40 PM, Aaron Durbin 
>>> wrote:
>>>
 On Wed, Feb 22, 2017 at 10:18 AM, Zoran Stojsavljevic
  wrote:
 > Aaron,
 >
 > Not that I am trying to be pest/bad guy. Please, believe me on this.
 Just
 > about the simple logic, which SHOULD NOT be deniable!
 >
 > I did what I know about Coreboot, hands on, from 3.3 years ago. Then,
 I
 > built the VERY first Emerald Lake 2 (CCG CRB) -> Cougar Canyon 2 CRB
 as
 > payload SeaBIOS, and WIN 8.0 32bit. I was really 

Re: [coreboot] Lenovo T420 Question

[qma ster]

Actually there is an even better non-conductive thermal paste (not liquid
metal) than "Grizzly" --- it is called " Gelid GC-Extreme ". Here is a
comparison from one review website that I screenshotted -
https://s4.postimg.org/qvp326pjx/Thermal_Grease.png  . The difference
between them is not big, but I think in your case every degree counts.
Also, there is a packaging of Gelid GC-Extreme that is 10g -
http://gelidsolutions.com/thermal-solutions/thermal-compound-gc-extreme-10g/
, this larger packaging gives a very affordable price per 1g and will last
for a long time ;)

2017-02-23 4:49 GMT+03:00 :

> Could you try out "Thermal Grizzly Kryonaut" or even liquid metal based
> products and report about the temperatures? It would be great if you could
> try out first the Thermal Grizzly Kryonaut and later then for example the
> Thermal Grizzly Conductonaut and report here.
> http://www.overclock.net/t/1588116/thermal-grizzly-conductonaut-73-w-mk
>
> Please clean up the surface before applying when possible with
> https://en.wikipedia.org/wiki/Isopropyl_alcohol (its cheap and easy to
> get).
>
> 23. Feb 2017 01:28 by coreb...@semioptimal.net:
>
>
> Hi
>
>
> Untested/unknown: If a ivy bridge CPU would work. The OEM bios didn't had
> support for those.
>
>
> Ivy Bridge works, have a 3740QM in mine. However, (quoting myself here):
>
>
> I'm running one albeit with an i7-3740qm - which is too much thermal load,
> runs up to 2.9 GHz for me reaching 93°C (70K to ambient) with fan set to
> disengaged, normal auto fan control works and allows up to 2.5 GHz.
>
> with that CPU RAPL does not work, thermald does but out-of-the-box
> settings gives me less performance than with fix limits, and I'm sure as
> hell not going to configure something with an xml config file.
>
> used to have a 2720m which worked without any issues AFAIR, but the 3740qm
> effectively gives me double the cores that are a little faster.
>
>
> Regards, Arian
>
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://www.coreboot.org/mailman/listinfo/coreboot
>
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[coreboot] Improving KBC1126 support for HP laptops

[Iru Cai]

Hi,

I'm now doing the port for HP Elitebook 2760p (
https://review.coreboot.org/#/c/18241/) and other HP laptops, but I'm now
having trouble with the EC+SuperIO chip KBC1126.

Now I can use superio/smsc/kbc1100 to enable keyboard support. However, I
still cannot access the EC with ectool, which will give me all 0xff when I
run `ectool -d`. Also I cannot use the touchscreen even I write some ACPI
code.

I have searched and downloaded two SMSC confidential document: a KBC1122
preliminary datasheet and a KBC1122 BIOS porting guide. Is there any
problem if I use them to write some code?

Thanks,
Iru

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Re: [coreboot] [VERY IMPORTANT] Announcement regarding Apollo Lake Coreboot building

[Zoran Stojsavljevic]

Hello Youness (and others),

Here, I need to apologize to all Coreboot recipients. Since it was a while,
I did peak into that. But... It is NOT You(ness). You got my attention,
and, since you blog is very confusing (lack of  some systematic knowledge)
about INTEL BSP Technology.

I really admire your effort. And just because of that I (after some 6+
hours of investigation) I'll try to strengthen out your logs, which are, I
should say, puzzled, scrambled all over place. Pieces of Truth are there,
and you got on the right path. Although... Labyrinth (unsorted kludges and
facts) for most of folks.

*I did NOT expect that ... will make out of this Rocket Science.* And yes,
they did make it??? Why, that is the question? ;-)

I got it. Not quite up to ground level (I need to understand more about
make menuconfig setup). But in order to make (example) 8MB Coreboot, you
need to take the TRUE APL-I BIOS and to apply IFD tool, in order to extract
first 4K (4096) File Descriptor. And SBIOS part as well. Not sure how many
parts should be extracted?!

Here is what GOOGLE designers posted for Emerald Lake 2, in 3rdparty:

[user@localhost emeraldlake2]$ ls -al
total 2120
drwxrwxr-x. 2 user user4096 Feb 18 01:57 .
drwxrwxr-x. 3 user user4096 Feb 18 01:57 ..
-rw-rw-r--. 1 user user   4096 Feb 18 01:57 descriptor.bin
-rw-rw-r--. 1 user user   2093056 Feb 18 01:57 me.bin
-rw-rw-r--. 1 user user   65536 Feb 18 01:57 snm_2120.dat
[user@localhost emeraldlake2]$ pwd
/home/intel/projects/coreboot/coreboot/3rdparty/blobs/
mainboard/intel/emeraldlake2
[user@localhost emeraldlake2]$

And, for descriptor.bin, there is the following:

[image: Inline image 1]

This (location 0x0010) I have checked with many BIOSes found on the
open net, . Most, but I did not find any instance of Apollo Lake, to build
proper Coreboot.com.

So, I need to extract at least SBIOS and descriptor.bin from real (UEFI)
BIOS, and put, where?

And then, to add to the Coreboot image. Using make menuconfig. Where and
how?

(Courtesy Aaron Durbin): http://elinux.org/Minnowboard:
MinnowMaxCoreboot#TXE_and_SPI_descriptor

Thank you all,
Zoran

On Thu, Feb 23, 2017 at 12:30 AM, Youness Alaoui <
kakar...@kakaroto.homelinux.net> wrote:

> Zoran, read this : https://puri.sm/posts/librem-13-coreboot-report-
> january-12-2017/
> It might help you understand what that IFD and 0x5aa5f00f is (little
> endian makes it 0x0FF0A55A)
> I had the same confusion when I started, and when I figured things out, I
> wrote that blog post that explained the process.
>
>
> On Wed, Feb 22, 2017 at 11:51 AM, Zoran Stojsavljevic <
> zoran.stojsavlje...@gmail.com> wrote:
>
>> So, the final word here: In building of INTEL skus' Coreboot INTEL FIT
>> tool (under NDA) is A MUST/mandatory, and INTEL is the road block if you
>> are not working with them (having the NDA signed with them)?
>>
>> What about the concept of an Open Source??? ;-)
>>
>> I am at this point very confused... Really, I am. I did NOT find anywhere
>> in any document that for Coreboot building INTEL FIT is mandatory???
>>
>> Thank you,
>> Zoran
>>
>> On Wed, Feb 22, 2017 at 5:40 PM, Aaron Durbin  wrote:
>>
>>> On Wed, Feb 22, 2017 at 10:18 AM, Zoran Stojsavljevic
>>>  wrote:
>>> > Aaron,
>>> >
>>> > Not that I am trying to be pest/bad guy. Please, believe me on this.
>>> Just
>>> > about the simple logic, which SHOULD NOT be deniable!
>>> >
>>> > I did what I know about Coreboot, hands on, from 3.3 years ago. Then, I
>>> > built the VERY first Emerald Lake 2 (CCG CRB) -> Cougar Canyon 2 CRB as
>>> > payload SeaBIOS, and WIN 8.0 32bit. I was really amazed. Then.
>>> >
>>> > And I read much more these days, and a bit emailed with Martin
>>> (forth/back),
>>> > so Martin can give me a jump start. And then I read more. And more.
>>> And for
>>> > 5 full days I was doing this exercise (with lot of pain).
>>> >
>>> > So, I'll quote you:
>>> >
>>> >> That file is the FSP blob. Nothing more. As Nico pointed out that is
>>> >> something completely different from the flash descriptor. The flash
>>> >> descriptor can be obtained from the original released BIOS or you have
>>> >> to generate it using Intel's FIT tool.
>>> >
>>> > Please, guide me through this process. Or point to some documents
>>> about this
>>> > process I can read about?
>>>
>>> IIRC, FIT is provided by Intel to its customers under NDA. You'll have
>>> to contact your Intel rep for that. It's quite the barrier to entry
>>> for using these devices, but that's a policy decision from Intel.
>>>
>>> Or you can take a previously released bios for this board and do
>>> similar as the instructions on the Minnow Max page:
>>> http://elinux.org/Minnowboard:MinnowMaxCoreboot#TXE_and_SPI_descriptor
>>>
>>> Note, TXE/CSE on apollolake does not have its own region in the flash.
>>> It's in something intel calls IFWI and has its own new format that
>>> lives in the "BIOS" region. There's a tool 

Re: [coreboot] Dont filter supported CPUs on a mainboard by the CPUID

[Aaron Durbin via coreboot]

On Thu, Feb 23, 2017 at 2:39 AM, Nico Huber  wrote:
> On 23.02.2017 00:07, i1w5d7gf38...@tutanota.com wrote:
>
>> There is a Filter to stop booting when the CPUID is not in a list of
>> supported CPUs. This filter does not make sense in the real world usage.
>
> It's not a filter. It's a measure to know which code to run for which
> CPU. Please dig a little deeper before making such useless complaints.

To add to Nico's point: the cpuid list is a way to bind code code to
run for certain devices -- including CPUs. If the cpuid is not listed
then the match on device->code to run is not met. Therefore, the code
necessary to make that CPU work won't ever be ran. src/arch/x86/cpu.c
has the cpu driver binding. And there already is message printed. See
the callers of set_cpu_ops() in that file. The issue is that we die()
when no match is found. We could attempt to boot further, but there's
no guarantee it'd actually succeed.

>
> Nico
>
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> https://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Coreboot on Thinkpad "X62" (i7-5600u)?

[Iru Cai]

Hello,

On Thu, Feb 23, 2017 at 3:46 PM, Rafael Send  wrote:

> Hello there-
> I'm assuming this is the right way to ask a general question, but please
> let me know if it isn't.
>
> I have an "X62" laptop, which is actually an old Thinkpad X61 with a
> custom motherboard in it.
> This board has an i7-5600u CPU on it, and I was wondering if it was
> possible to build a version of coreboot for this machine.
> I see an existing mailing list entry in the archive discussing a
> Chromebook Pixel with the same CPU, so I'm thinking it may be possible
> unless I'm missing something major.
> Since this is a custom motherboard, how would I find out about the Intel
> Boot Guard and related issues so that I can provide the details for the
> good folks here?
>

You can try https://review.coreboot.org/#/c/16328/, or modify some
instructions in the firmware to see if it still boots.

If boot guard is not enabled, I think booting with coreboot is not so hard,
but it may be hard to make the EC interface work fine.

Iru

I'm pretty comfortable around Linux but probably would have trouble
> building this from scratch.
> Thanks in advance!
>
> Rafael
>
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> https://www.coreboot.org/mailman/listinfo/coreboot
>



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[coreboot] Coreboot on Thinkpad "X62" (i7-5600u)?

[Rafael Send]

Hello there-
I'm assuming this is the right way to ask a general question, but please
let me know if it isn't.

I have an "X62" laptop, which is actually an old Thinkpad X61 with a custom
motherboard in it.
This board has an i7-5600u CPU on it, and I was wondering if it was
possible to build a version of coreboot for this machine.
I see an existing mailing list entry in the archive discussing a Chromebook
Pixel with the same CPU, so I'm thinking it may be possible unless I'm
missing something major.
Since this is a custom motherboard, how would I find out about the Intel
Boot Guard and related issues so that I can provide the details for the
good folks here?
I'm pretty comfortable around Linux but probably would have trouble
building this from scratch.
Thanks in advance!

Rafael
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Re: [coreboot] T520 2630QM 16GB DIMM

[Nico Huber]

On 23.02.2017 01:33, i1w5d7gf38...@tutanota.com wrote:

> It would be really great if you could test out a Core i7-3840QM in the
> G2 socket of the Thinkpad T520. Its the best ivy bridge with 45W TDP and
> the Core i7-3840QM officialy support 32GB of RAM.

Only with 8 ranks of 4GiB. That would be 4 8GiB SO-DIMMs, good luck
squeezing them into a T520.

Nico

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