Re: [coreboot] Asus M2N-E

Hi Mike, I use Cutecom. Why ? Martin De : Mike Banon Envoyé : lundi 5 juin 2017 17:03 À : Martin A Objet : Re: [coreboot] Asus M2N-E Hi Martin! Please tell: what tools are you using to receive this coreboot booting log? On Wed, May 24,

Re: [coreboot] make crossgcc-i386 : ubsan.c error (with fix!) for GCC

Hi, Le dimanche 04 juin 2017 à 22:49 +, qma ster a écrit : > Good day! While building the coreboot's toolchain by using GCC 7.1.1 > version, I am getting the following error: […] > Found this solution here - > https://patchwork.openembedded.org/patch/138884/ . Would be great if > you could

Re: [coreboot] VT-d support

On 05.06.2017 19:47, Zoran Stojsavljevic wrote: >> If you are lucky, you only need to add 20~30 lines to your chipset's code. > > Could you, please, show us an explicit example (of these 20 to 30 lines of > code)?! `src/northbridge/intel/sandybridge/iommu.c` and acpi_fill_dmar() in

Re: [coreboot] VT-d support

> If you are lucky, you only need to add 20~30 lines to your chipset's code. Could you, please, show us an explicit example (of these 20 to 30 lines of code)?! Zoran On Mon, Jun 5, 2017 at 7:34 PM, Nico Huber wrote: > Hi, > > On 05.06.2017 18:58, Himanshu Chauhan wrote: > > >

Re: [coreboot] What does *intelblocks* mean?

>> The reason 'intelblocks' is in the include path is because the include >> headers are namespaced. e.g. #include . My +2 to Aaron's comment, that’s the only reason to create "intelblocks". Thanks, Subrata -Original Message- From: Aaron Durbin [mailto:adur...@google.com] Sent:

Re: [coreboot] VT-d support

On Mon, Jun 5, 2017 at 10:33 AM Himanshu Chauhan wrote: > > > oh, really? Why do you think that? Have you looked at the relevant MSR > and what is the basis of your claim? > > I was just guessing what it could be. :) > > I think it's a ton easier if you study on some

Re: [coreboot] VT-d support

> On 05-Jun-2017, at 10:50 PM, ron minnich wrote: > > > > On Mon, Jun 5, 2017 at 9:58 AM Himanshu Chauhan > wrote: > > I think its can’t just be disabled. > > oh, really? Why do you think that? Have you looked at the relevant MSR and > what is

Re: [coreboot] VT-d support

Hi, On 05.06.2017 18:58, Himanshu Chauhan wrote: > >> On 05-Jun-2017, at 10:19 PM, ron minnich wrote: >> >> The reason I ask about what you need is that on chromebooks the main >> coreboot support came down to 'don't disable anything’. > > I think its can’t just be

Re: [coreboot] VT-d support

On Mon, Jun 5, 2017 at 9:58 AM Himanshu Chauhan wrote: > > I think its can’t just be disabled. > oh, really? Why do you think that? Have you looked at the relevant MSR and what is the basis of your claim? ron -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] VT-d support

> On 05-Jun-2017, at 10:19 PM, ron minnich wrote: > > The reason I ask about what you need is that on chromebooks the main coreboot > support came down to 'don't disable anything’. I think its can’t just be disabled. Its just that kernel is not given any knowledge about

Re: [coreboot] VT-d support

The reason I ask about what you need is that on chromebooks the main coreboot support came down to 'don't disable anything'. The DMAR requirements are not met on all platforms. But even after boot you can insert DMAR tables into kernels. So there is a key distinction between required support and

Re: [coreboot] VT-d support

> On 05-Jun-2017, at 10:02 PM, Zaolin wrote: > > You are asking for VT-d support. You are talking about Intel platforms ? Yes. I am talking about intel platforms. All CPUs that have VT-d support need support from motherboards as well. So any setup with VT-d enabled CPU

Re: [coreboot] VT-d support

> what support does it need? Intel Virtualization Technology for Directed I/O" (VT-d). VT-d is a virtualized IOMMU, so by using HYP type 1 there should be a VT-d driver supporting VT-d HW extension (?), as my best understanding is The practical implications are Graphics and Network Connectivity

Re: [coreboot] VT-d support

You are asking for VT-d support. You are talking about Intel platforms ? But for which specific platform you are asking for ? There are so many.. Am 05.06.2017 um 10:24 schrieb Himanshu Chauhan: > >> On 05-Jun-2017, at 9:41 PM, ron minnich wrote: >> >> >> >> On Mon, Jun 5,

Re: [coreboot] VT-d support

> On 05-Jun-2017, at 9:41 PM, ron minnich wrote: > > > > On Mon, Jun 5, 2017 at 9:00 AM Himanshu Chauhan > wrote: > Hi, > > VT-d requires support from BIOS. Does coreboot support VT-d? > > > > what support does it need? BIOS adds DMAR and

Re: [coreboot] VT-d support

On Mon, Jun 5, 2017 at 9:00 AM Himanshu Chauhan wrote: > Hi, > > VT-d requires support from BIOS. Does coreboot support VT-d? > > > what support does it need? -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] VT-d support

Hi, VT-d requires support from BIOS. Does coreboot support VT-d? Regards Himanshu Chauhan -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] What does *intelblocks* mean?

On Mon, Jun 5, 2017 at 2:48 AM, Paul Menzel wrote: > Dear coreboot folks, > > > In commit a554b0c5b7 (soc/intel/common/block: Add Intel XHCI driver > support) [1] the directory > `src/soc/intel/common/block/include/intelblocks` is created. > > Could somebody

Re: [coreboot] Current, BLOB free laptop available Europe?

actually Lenovo G505S has more freedom in some relations, if compared to Chromebook R13 : for example, G505S does not require blobs for WiFi and Bluetooth if you replace its' preinstalled Broadcom half size mini PCI-e card with Atheros AR9462 (which has 2.4 GHz + 5 GHz + Bluetooth and is

[coreboot] MRC Raminit

Hi, I am working on an embedded board from Interface concept. The chipset is intel QM67 (Cougar point) with a sandybridge Gen2 processor. I think the board doesn’t have any spd because I get the error “Not a DDR3 SPD!” so I try to do the mrc raminit with the systemagent-r6.bin but I am stuck on

[coreboot] What does *intelblocks* mean?

Dear coreboot folks, In commit a554b0c5b7 (soc/intel/common/block: Add Intel XHCI driver support) [1] the directory `src/soc/intel/common/block/include/intelblocks` is created. Could somebody please help me, what *intelblocks* means here, and why *intel* is twice in the path? Thanks, Paul