date:20171003

Re: [coreboot] Intel Leaf Hill Coreboot Trouble

2017-10-03 Thread Cameron Craig

Hi all,

I have enabled post codes and all the debug config options in coreboot that 
looked useful.

As Paul has already done, I have narrowed down the latest issue to the 
FspSiliconInit() stage (FSP-S).
The 0x93 post code is the last message I get on the serial console, and 
signifies that FspSiliconInit() has started but not completed.
See 
(https://github.com/coreboot/coreboot/blob/master/src/include/console/post_codes.h).

I have attached the full serial log.

I can’t see how the actual FSP blob could be at fault here.

I don’t know if this is of help, but I came across this document:
https://github.com/IntelFsp/FSP/raw/ApolloLake/ApolloLakeFspBinPkg/Docs/Apollo_Lake_FSP_Integration_Guide.pdf

Specifically section 3.5.4:
“It is expected that boot loader will program MTRRs for SBSP as needed after 
TempRamExit but before entering FspSiliconInit. If MTRRs are not programmed 
properly, the boot performance might be impacted.”

This “boot performance” may be part of the issue?

Any thoughts would be appreciated, this mailing list has been helpful so far!

Cheers,
Cameron




Cameron Craig | Graduate Software Engineer | Exterity Limited
tel: +44 1383 828 250 | fax:
e: cameron.cr...@exterity.com | w: www.exterity.com




From: Cameron Craig
Sent: 02 October 2017 11:19
To: Cameron Craig; 'Paul Penz'; coreboot@coreboot.org
Subject: RE: Re: [coreboot] Intel Leaf Hill Coreboot Trouble

Hi Paul,

Those changes to the IFWI blob worked great, thanks!
I have attached the serial console log. It looks like we are in similar 
situations now.

I got a hang of around 45s at “MRC: region file invalid in 'RW_VAR_MRC_CACHE”,
and then it hangs indefinitely at the end of the log.

I tracked the MRC cache message down to this line:
https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/mrc_cache.c#L272

I’m stuck again for the moment. Thanks again Paul for getting me one step 
closer.

Cheers,
Cameron

From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Cameron Craig
Sent: 28 September 2017 16:51
To: 'Paul Penz'; coreboot@coreboot.org
Subject: Re: [coreboot] Intel Leaf Hill Coreboot Trouble

Hi Paul,

Great to hear I’m not the only one in this situation ☺

I’ve just been using the IWFI file from Intel with no modifications,  so I’ll 
look out the FIT tool and give that a go.

Thanks,
Cameron




Cameron Craig | Graduate Software Engineer | Exterity Limited
tel: +44 1383 828 250 | fax:
e: cameron.cr...@exterity.com | w: 
www.exterity.com


From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Paul Penz
Sent: 28 September 2017 15:35
To: coreboot@coreboot.org
Subject: Re: [coreboot] Intel Leaf Hill Coreboot Trouble

Hi Cameron,

I had the same problem.

Had you modified the intel IFWI file ?

If not, I had done this additional:

Download 522538_apl txe hf 3.0.11.1131 (th2 & rs1).zip from intel
Start fit.exe
Load the IFWI file
Change at Platform Protection/Platform Integrity OOEM Public Key Hash => 00..00
Change at Platform Protection/Boot Guard Configuration/ Boot profile 2 => 0
Save

Now I get output on the console and postcodes, but during FSP_M a long pause of 
ca. 45s exists and it hangs later during FSP_P initialization.

Good luck
Paul



Paul Penz
Dipl.-Ing. (FH)
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ELTEC Elektronik AG, Mainz
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[coreboot] What’s the release plan for coreboot 4.7?

2017-10-03 Thread Paul Menzel

Dear coreboot folks,


It’s October and coreboot 4.7 is supposed to be tagged in this month.

Are there more specific plans already, when the release will happen?


Thanks,

Paul

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Re: [coreboot] [ANN] ECC 2017: Schedule and speakers published

2017-10-03 Thread Zaolin

Sure. All talks will be recorded and afterwards uploaded to our youtube
channel ;)


On 03.10.2017 14:09, Rene Shuster wrote:
> Same here. Recorded presentations for later stream/download would be
> very much appreciated.
>
> On Tue, Oct 3, 2017 at 7:42 AM, Rafael Machado
>  > wrote:
>
> Hi everyone
>
> Quick question. 
> I'm really interested on the presentations, but will not be able
> to be present at the event.
> Will the presentations be recorded and posted at some place later?
>
> Thanks and Regards
> Rafael R. Machado
>
>
> Em ter, 3 de out de 2017 às 06:37, Paul Menzel
>  > escreveu:
>
> Dear coreboot folks,
>
>
> I’d like to inform you that the schedule for the European coreboot
> conference was published and the speakers were announced [1].
>
> A big thanks to everybody sending in proposals and to the program
> committee.
>
> Now, please spread the word, buy tickets, and plan your trip. I am
> looking forward to see you all in Bochum.
>
>
> Thanks,
>
> Paul
>
>
> [1] https://ecc2017.coreboot.org/schedule-location
> --
> coreboot mailing list: coreboot@coreboot.org
> 
> https://mail.coreboot.org/mailman/listinfo/coreboot
> 
>
>
> --
> coreboot mailing list: coreboot@coreboot.org
> 
> https://mail.coreboot.org/mailman/listinfo/coreboot
> 
>
>
>
>
> -- 
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>
>



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Re: [coreboot] How to work with Chrome EC? (was: Successful build with GCC 7.2 and IASL 20170831 for coreboot 4.7)

2017-10-03 Thread Vadim Bendebury

yes, there is not much special about Chrome OS chroot, but it makes things
easier and applies the pre-upload checks if the repo utility is used. The
same checks could be run manually, and outside chroot, but this would
require some discipline.

I mentioned cros sdk because Paul said he was missing the repo  manifest.

--vb


On Tue, Oct 3, 2017 at 2:10 AM, Paul Kocialkowski  wrote:

> Hi,
>
> Le lundi 02 octobre 2017 à 13:47 -0700, Vadim Bendebury a écrit :
> > the entry threshold is a big high, but I am sure the Chome OS EC team
> would
> > appreciate your contributions.
>
> Actually, I have been contributing to various Chromium OS project over the
> years
> and never had to setup the whole cros environment.
>
> Not only is it possible to build the software outside of the cros build
> system
> (e.g. such as it's done in the coreboot build system directly or through my
> build system[0]), but it's also possible to send patches for review
> without it.
>
> The Chromium Review Gerrit[1] works pretty much like the coreboot one,
> except
> that it may use https and a cookie rather than ssh and a pubkey for
> pushing. So
> once the account is setup on Gerrit (requires a Google account AFAIK), you
> can
> simply push to projects like that:
>
> git push https://chromium-review.googlesource.com/chromiumos/platform/ec
> master:refs/for/master
>
> And that usually works well for me. Just keep in mind that you need to
> include
> custom tags, such as Change-Id, TEST= and BUG= in the commit message.
>
> Cheers,
>
> Paul
>
> [0]: https://git.code.paulk.fr/gitweb/?p=libettereboot.git;a=summary
> [1]: https://chromium-review.googlesource.com/
>
> > On Mon, Oct 2, 2017 at 12:04 AM, Paul Menzel  sourceforge.ne
> > t> wrote:
> > > Dear coreboot folks,
> > >
> > >
> > > GCC 7.2 found several issues in the Chromium EC code base, like #770209
> > > [4], and I prepared  patches, but unfortunately, I do not know how to
> > > push them for review.
> > >
> > > 1. The instructions don’t work for me [5]. I can’t find the manifest
> > > file, which seems to be required by the utility `repo`.
> > >
> > > 2. Also, in the preferences menu of the Google Chromium review system,
> > > I cannot find a way to upload my SSH key.
> > >
> > > 3. Is there a mailing list for the Chromium Embedded Controller
> > > development?
> > >
> > >
> > > Thanks,
> > >
> > > Paul
> > >
> > >
> > > [4] https://bugs.chromium.org/p/chromium/issues/detail?id=770209
> > > [5] https://dev.chromium.org/chromium-os/ec-development
> > > [6] https://chromium-review.googlesource.com/admin/
> projects/chromiumos/platf
> > > orm/ec,access
> > > --
> > > coreboot mailing list: coreboot@coreboot.org
> > > https://mail.coreboot.org/mailman/listinfo/coreboot
> >
> >
> --
> Paul Kocialkowski, developer of free digital technology and hardware
> support
>
> Website: https://www.paulk.fr/
> Coding blog: https://code.paulk.fr/
> Git repositories: https://git.paulk.fr/ https://git.code.paulk.fr/
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Re: [coreboot] [RFC] Successful build with GCC 7.2 and IASL 20170831 for coreboot 4.7

2017-10-03 Thread Martin Roth

I'd say that it doesn't make sense to require that coreboot builds
with anything other than the coreboot toolchain.
Additionally, It isn't reasonable to introduce a new requirement this
close to the release.

Martin

On Wed, Sep 20, 2017 at 12:17 AM, Paul Menzel
 wrote:
> Dear coreboot folks,
>
>
> I’d like to propose the following goal for the upcoming coreboot 4.7
> release.
>
> All boards have to build with GCC 7.2 [1] and IASL 20170831 [2].
>
> For the latter, several Intel boards fail to build [3]. It’d be great
> if the maintainers looked into it.
>
>
> Thanks,
>
> Paul
>
>
> [1] https://review.coreboot.org/20809/
> [2] https://review.coreboot.org/21156/
> [3] https://ticket.coreboot.org/issues/138
> --
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> https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] [ANN] ECC 2017: Schedule and speakers published

2017-10-03 Thread Rene Shuster

Same here. Recorded presentations for later stream/download would be very
much appreciated.

On Tue, Oct 3, 2017 at 7:42 AM, Rafael Machado <
rafaelrodrigues.mach...@gmail.com> wrote:

> Hi everyone
>
> Quick question.
> I'm really interested on the presentations, but will not be able to be
> present at the event.
> Will the presentations be recorded and posted at some place later?
>
> Thanks and Regards
> Rafael R. Machado
>
>
> Em ter, 3 de out de 2017 às 06:37, Paul Menzel  sourceforge.net> escreveu:
>
>> Dear coreboot folks,
>>
>>
>> I’d like to inform you that the schedule for the European coreboot
>> conference was published and the speakers were announced [1].
>>
>> A big thanks to everybody sending in proposals and to the program
>> committee.
>>
>> Now, please spread the word, buy tickets, and plan your trip. I am
>> looking forward to see you all in Bochum.
>>
>>
>> Thanks,
>>
>> Paul
>>
>>
>> [1] https://ecc2017.coreboot.org/schedule-location--
>> coreboot mailing list: coreboot@coreboot.org
>> https://mail.coreboot.org/mailman/listinfo/coreboot
>
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot
>



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Re: [coreboot] [ANN] ECC 2017: Schedule and speakers published

2017-10-03 Thread Rafael Machado

Hi everyone

Quick question.
I'm really interested on the presentations, but will not be able to be
present at the event.
Will the presentations be recorded and posted at some place later?

Thanks and Regards
Rafael R. Machado


Em ter, 3 de out de 2017 às 06:37, Paul Menzel <
paulepan...@users.sourceforge.net> escreveu:

> Dear coreboot folks,
>
>
> I’d like to inform you that the schedule for the European coreboot
> conference was published and the speakers were announced [1].
>
> A big thanks to everybody sending in proposals and to the program
> committee.
>
> Now, please spread the word, buy tickets, and plan your trip. I am
> looking forward to see you all in Bochum.
>
>
> Thanks,
>
> Paul
>
>
> [1] https://ecc2017.coreboot.org/schedule-location--
> coreboot mailing list: coreboot@coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot
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[coreboot] Ability to remotely debug the grub menu in case of boot failure

2017-10-03 Thread Anshuman Aggarwal

Hi,
If a coreboot compatible motherboard is used and the right
coreboot+plugins flashed, is there a way that can be used to view the
linux terminal console during boot time in order to remotely
debug/troubleshoot any grub level bootup issues (before the SSH or any
other such daemon can load)?

All the solutions I see so far seem to be proprietary to Intel and
require Server motherboards.

Since coreboot has a network debug log sending option, it stands to
reason that it could theoretically connecting a terminal console over
a compatible ethernet card?

Thoughts anyone? Apologies if this has been asked but mailman does not
make it easy to search archives.

Regards
Anshuman

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[coreboot] [ANN] ECC 2017: Schedule and speakers published

2017-10-03 Thread Paul Menzel

Dear coreboot folks,


I’d like to inform you that the schedule for the European coreboot
conference was published and the speakers were announced [1].

A big thanks to everybody sending in proposals and to the program
committee.

Now, please spread the word, buy tickets, and plan your trip. I am
looking forward to see you all in Bochum.


Thanks,

Paul


[1] https://ecc2017.coreboot.org/schedule-location

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Re: [coreboot] How to work with Chrome EC? (was: Successful build with GCC 7.2 and IASL 20170831 for coreboot 4.7)

2017-10-03 Thread Paul Kocialkowski

Hi,

Le lundi 02 octobre 2017 à 13:47 -0700, Vadim Bendebury a écrit :
> the entry threshold is a big high, but I am sure the Chome OS EC team would
> appreciate your contributions.

Actually, I have been contributing to various Chromium OS project over the years
and never had to setup the whole cros environment.

Not only is it possible to build the software outside of the cros build system
(e.g. such as it's done in the coreboot build system directly or through my
build system[0]), but it's also possible to send patches for review without it.

The Chromium Review Gerrit[1] works pretty much like the coreboot one, except
that it may use https and a cookie rather than ssh and a pubkey for pushing. So
once the account is setup on Gerrit (requires a Google account AFAIK), you can
simply push to projects like that:

git push https://chromium-review.googlesource.com/chromiumos/platform/ec 
master:refs/for/master

And that usually works well for me. Just keep in mind that you need to include
custom tags, such as Change-Id, TEST= and BUG= in the commit message.

Cheers,

Paul

[0]: https://git.code.paulk.fr/gitweb/?p=libettereboot.git;a=summary
[1]: https://chromium-review.googlesource.com/

> On Mon, Oct 2, 2017 at 12:04 AM, Paul Menzel  t> wrote:
> > Dear coreboot folks,
> > 
> > 
> > GCC 7.2 found several issues in the Chromium EC code base, like #770209
> > [4], and I prepared  patches, but unfortunately, I do not know how to
> > push them for review.
> > 
> > 1. The instructions don’t work for me [5]. I can’t find the manifest
> > file, which seems to be required by the utility `repo`.
> > 
> > 2. Also, in the preferences menu of the Google Chromium review system,
> > I cannot find a way to upload my SSH key.
> > 
> > 3. Is there a mailing list for the Chromium Embedded Controller
> > development?
> > 
> > 
> > Thanks,
> > 
> > Paul
> > 
> > 
> > [4] https://bugs.chromium.org/p/chromium/issues/detail?id=770209
> > [5] https://dev.chromium.org/chromium-os/ec-development
> > [6] https://chromium-review.googlesource.com/admin/projects/chromiumos/platf
> > orm/ec,access
> > --
> > coreboot mailing list: coreboot@coreboot.org
> > https://mail.coreboot.org/mailman/listinfo/coreboot
> 
> 
-- 
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Website: https://www.paulk.fr/
Coding blog: https://code.paulk.fr/
Git repositories: https://git.paulk.fr/ https://git.code.paulk.fr/

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Re: [coreboot] [RFC] Successful build with GCC 7.2 and IASL 20170831 for coreboot 4.7

2017-10-03 Thread Williams, Hannah

Hi Matt,
Thanks for looking into this.
Please submit the patch since you have identified the issue.
Thanks
Hannah Williams

From: Matt DeVillier [mailto:matt.devill...@gmail.com]
Sent: Monday, October 2, 2017 8:51 PM
To: Paul Menzel 
Cc: coreboot ; Williams, Hannah 

Subject: Re: [coreboot] [RFC] Successful build with GCC 7.2 and IASL 20170831 
for coreboot 4.7

hi Paul,

I took a look at this, and the error appears to be the result of a change in 
IASL 20170531:

"Improved the behavior of the iASL compiler and disassembler to detect improper 
use of external declarations"

According to the ACPI 6.2 spec, "The External directive informs the ASL 
compiler that the object is declared external to this table.."  This reads to 
me that if an object is declared External in one table (eg, the DSDT), then its 
declaration must be in another table, not in the table in which contains the 
External reference.  As _SB.DPTF.TEVT is declared in the DSDT (in SoC .asl 
code), then the External declaration in the chromeec/acpi/ec.asl is invalid.

To test this, I removed the External declaration in ec.asl, and the previously 
failing boards now build properly with iASL 20170831.  I also retested using 
the current iASL version (20161222), and the aforementioned boards still build 
correctly.

If someone wants to corroborate my analysis, then I'm happy to submit a patch 
to correct the issue

cheers,
Matt

On Mon, Oct 2, 2017 at 1:56 AM, Paul Menzel 
> 
wrote:
Dear coreboot folks,

Am Mittwoch, den 20.09.2017, 08:17 +0200 schrieb Paul Menzel:

> I’d like to propose the following goal for the upcoming coreboot 4.7
> release.
>
> All boards have to build with GCC 7.2 [1] and IASL 20170831 [2].
>
> For the latter, several Intel boards fail to build [3]. It’d be great
> if the maintainers looked into it.

Unfortunately, there was no reply yet. Patrick already blocked the
change-set, and commented that it’ll only go in after the coreboot 4.7
release, which is fine. But the boards should still build in my
opinion.

The boards below are affected by the IASL update.

```
$ git grep TEVT
src/ec/google/chromeec/acpi/ec.asl:External (\_SB.DPTF.TEVT, MethodObj)
src/ec/google/chromeec/acpi/ec.asl: If (CondRefOf 
(\_SB.DPTF.TEVT)) {
src/ec/google/chromeec/acpi/ec.asl: \_SB.DPTF.TEVT 
(Local0)
src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl:Method
 (TEVT, 1, NotSerialized)
src/soc/intel/baytrail/acpi/dptf/thermal.asl:Method (TEVT, 1, NotSerialized)
src/soc/intel/braswell/acpi/dptf/thermal.asl:Method (TEVT, 1, NotSerialized)
src/soc/intel/common/acpi/dptf/thermal.asl:Method (TEVT, 1, NotSerialized)
src/soc/intel/skylake/acpi/dptf/thermal.asl:Method (TEVT, 1, NotSerialized)
```

What is the process for this? Are the maintainers of the board that
fail to build subscribed on this mailing list?

Kind regards,

Paul

> [1] https://review.coreboot.org/20809/
> [2] https://review.coreboot.org/21156/
> [3] https://ticket.coreboot.org/issues/138

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[coreboot] Broadwell-DE NS FSP not support

2017-10-03 Thread 杜睿哲_Pegatron

Hi,
I have an Intel Broadwell-DE NS CRB and I want to evaluate it with coreboot. 
But from Intel FSP git, there is no corresponding FSP for Broadwell-DE NS. Does 
that mean I can’t use coreboot as boot loader if Intel FSP not available for my 
platform? If not, does anyone know how to do that? Please help. Thanks.
-Hilbert
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Re: [coreboot] Intel Leaf Hill Coreboot Trouble

[coreboot] What’s the release plan for coreboot 4.7?

Re: [coreboot] [ANN] ECC 2017: Schedule and speakers published

Re: [coreboot] How to work with Chrome EC? (was: Successful build with GCC 7.2 and IASL 20170831 for coreboot 4.7)

Re: [coreboot] [RFC] Successful build with GCC 7.2 and IASL 20170831 for coreboot 4.7

Re: [coreboot] [ANN] ECC 2017: Schedule and speakers published

Re: [coreboot] [ANN] ECC 2017: Schedule and speakers published

[coreboot] Ability to remotely debug the grub menu in case of boot failure

[coreboot] [ANN] ECC 2017: Schedule and speakers published

Re: [coreboot] How to work with Chrome EC? (was: Successful build with GCC 7.2 and IASL 20170831 for coreboot 4.7)

Re: [coreboot] [RFC] Successful build with GCC 7.2 and IASL 20170831 for coreboot 4.7

[coreboot] Broadwell-DE NS FSP not support

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